Makefile
3.44 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
# Makefile v1 Frank Berndt
# top level hardware-only makefile.
BBDEPTH = .
# Directory to store verilog output files (sim and c files).
# User can overide this variable on make command line, ie.
# 'make SIMDIR=/tmp' or environment variable.
SIMDIR ?= .
# simulator definitions;
SIMDEFS ?=
# paths to vendor library;
VLIB = lib/verilog
# path to bcp pli library;
LIBBCPPLI = $(BBDEPTH)/../../lib/libbcppli
# C compiler options
OPTIMIZER = -g
LCOPTS = -fullwarn
# all vcs dirt;
VCSDIRT = vcs.log \
$(SIMDIR)/c.*
# vcs options for behavioral simulator;
VCSOPTS = \
-l vcs.log \
-M -Mupdate \
$(SIMDEFS) \
+define+SIMCPU \
-V \
-y $(BBDEPTH) \
-y $(BBDEPTH)/bcp/src \
-y $(BBDEPTH)/bcp/rdp/src \
-y $(BBDEPTH)/bcp/ri/src \
-y $(BBDEPTH)/bcp/rsp/src \
-y $(BBDEPTH)/bcp/ar/src \
-y $(BBDEPTH)/bcp/mi/src \
-y $(BBDEPTH)/bcp/vi/src \
-y $(BBDEPTH)/bcp/ui/src \
-y $(BBDEPTH)/bcp/ai/src \
-y $(BBDEPTH)/bcp/pi/src \
-y $(BBDEPTH)/bcp/si/src \
-y $(BBDEPTH)/bcp/cs/src \
-y $(BBDEPTH)/bcp/ew/src \
-y $(BBDEPTH)/bcp/ep/src \
-y $(BBDEPTH)/bcp/cv/src \
-y $(BBDEPTH)/bcp/st/src \
-y $(BBDEPTH)/bcp/tc/src \
-y $(BBDEPTH)/bcp/tm/src \
-y $(BBDEPTH)/bcp/tf/src \
-y $(BBDEPTH)/bcp/cc/src \
-y $(BBDEPTH)/bcp/bl/src \
-y $(BBDEPTH)/bcp/at/src \
-y $(BBDEPTH)/bcp/bl/src \
-y $(BBDEPTH)/bcp/ms/src \
-y $(BBDEPTH)/bcp/rsp/src \
-y $(BBDEPTH)/bcp/su/src \
-y $(BBDEPTH)/bcp/vu/src \
-y $(BBDEPTH)/bcp/ls/src \
-y $(BBDEPTH)/bcp/io/src \
-y $(BBDEPTH)/bcp/sb/src \
-y $(BBDEPTH)/bcp/jtag/src \
-y $(BBDEPTH)/src \
-y $(BBDEPTH)/$(VLIB)/jlib \
-y $(BBDEPTH)/$(VLIB)/r4300 \
-y $(BBDEPTH)/$(VLIB)/nec \
-y $(BBDEPTH)/$(VLIB)/nec.15/verilog_udp \
-y $(BBDEPTH)/$(VLIB)/nec.15/special \
-y $(BBDEPTH)/$(VLIB)/nec.15/primitive \
-y $(BBDEPTH)/$(VLIB)/nec.15/clockdriver \
-y $(BBDEPTH)/$(VLIB)/nec.15/iobuffer \
-y $(BBDEPTH)/$(VLIB)/nec.15/memories \
-y $(BBDEPTH)/$(VLIB)/nec.15/oscillator \
-y $(BBDEPTH)/$(VLIB)/nec.15/scan \
-v $(BBDEPTH)/$(VLIB)/ricoh_encoder/A5C382CORE.v \
-y $(BBDEPTH)/$(VLIB)/usb_pad \
-y $(BBDEPTH)/$(VLIB)/virage \
-y $(BBDEPTH)/$(VLIB)/virage/NMS_16x32 \
-y $(BBDEPTH)/$(VLIB)/virage/NMS_64x32 \
-y $(BBDEPTH)/lib/usb_arc/verilog \
-y $(BBDEPTH)/lib/cast/aes_cbc_d/src \
+libext+.v+.vp+.VP+.vzd+.vmd \
+incdir+$(BBDEPTH)/include \
+incdir+$(BBDEPTH)/bcp/su/src \
+incdir+$(BBDEPTH)/bcp/vu/src \
+incdir+$(BBDEPTH)/bcp/ms/src \
+incdir+$(BBDEPTH)/lib/usb_arc/verilog
# synthesis files;
SYNFILES = \
syn/master/common/*.scr \
syn/master/common/*.setup \
syn/master/bb/script/*.scr \
syn/master/bb/report/Makefile
# target is top level bb;
TARGETS = help
default: $(TARGETS)
# help
help: _always
@echo "clean - clean up all vcs temporaries"
@echo "nec.tar - package files for NEC"
@echo "sim.v - vcs build of rtl"
# clean all vcs files;
clean-vcs: _always
$(RM) -rf $(VCSDIRT)
# thorough clean;
clean: clean-vcs
# package rtl files for NEC;
nec.tar: _always
tar cf $@ \
Makefile \
lib/verilog/ricoh_encoder/A5C382CORE.v \
$(SYNFILES) \
`find \
include bcp src \
lib/verilog/jlib \
lib/verilog/usb_pad \
lib/verilog/virage \
lib/usb_arc/verilog \
lib/cast/aes_cbc_d/src \
\( -name '*.v*' -o -name '*.h' \) \
-print`
# compile the behavioral simulator;
sim.v: _always
vcs $(VCSOPTS) \
-Mdir=$(SIMDIR)/c.v \
-P $(LIBBCPPLI)/bcppli.tab $(LIBBCPPLI)/libbcppli.a \
-o $(SIMDIR)/$@ \
src/bb.v
# always dependency;
_always: