/**************************************************************/
/*    Verilog module of datapath cell dpdff1101              */
/*    Designed by    Chunling Liu    Compass  Aug. 4, 92     */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        D    : the input port                               */
/*        Z    : the output port                              */
/*    Control ports                                           */
/*        INST_CP    : the clock signal                       */
/*        INST_OE    : load  enable                           */
/*        INST_INIT  : initialization control input           */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpdff1101(D, Z, INST_CP, INST_INIT, INST_OE);

  parameter WORDSIZE = 8, initial_value = 'b00000000, DELAY = 3, BF = 1;
  input  [WORDSIZE-1:0] D;
  output [WORDSIZE-1:0] Z;
  input  INST_CP, INST_INIT, INST_OE;

  reg    [WORDSIZE-1:0] Z;

  initial begin
          Z = {WORDSIZE{1'bx}};
          end

  always @ ( posedge INST_CP )
           begin
               Z = #DELAY ~(~D);
               if ( !INST_INIT )
                   #DELAY assign Z = initial_value;
               if ( !INST_OE )
                   #DELAY assign Z = {WORDSIZE {1'bz}};
           end

  always @ ( INST_INIT )
                if ( !INST_INIT )
                   #DELAY assign Z = initial_value;
                else
                   #DELAY deassign Z;

  always @ ( INST_OE )
                if ( !INST_OE )
                   #DELAY assign Z = {WORDSIZE {1'bz}};
                else
                   #DELAY deassign Z;

endmodule