/*******************************************************************************

-- File Type:    Verilog HDL 
-- Tool Version: VHDL2verilog  v4.4 Tue Sep 19 10:06:32 EDT 2000 SunOS 5.5.1 
-- VHDL translation of package (except components) 'vusb_cfg'

*******************************************************************************/
//  VUSB32_REV is used for the read only REV (revision) field of the build coniguration
//  peripheral revision register. 
//  3.0 coresponds to release 3.0 of the VUSB32-OTG core.
//  LOW_SPEED_DEVICE is used by the DPLLNRZI module in the testbench
//  host controller to determine the polarity of the dplus and dminus
//  signals for the J, K and SE0 USB states.  When set to 1 it
//  configures the logic as a low speed device:
//    K state = {dminus low, dplus high}
//    J state = {dminus high, dplus low}
//  Note that for a low speed device the input clock (usbclkx4) needs
//  to be 6MHz.
// When set to 0 it configures the logic for a high speed device.
//    K state = {dminus high, dplus low}
//    J state = {dminus low, dplus high}
//  Note that for a high speed device the input clock (usbclkx4) needs
//  to be 48MHz.
parameter VUSB32_REV = 8'b 00110000; //  30 (3.0)
parameter LOW_SPEED_DEV = 0; //  high speed device
//  The LOW_SPEED_DEV is separate from the low_speed_en signal that allows 
//  A full speed host or target to take on the signalling of a low speed
//  device dynamically.
//  IMPLEMENT_EMBEDED_HOST is used within the VUSB core in the usb_sie, and the
//  up_int to automatically allow or remove gates associated with the embeded
//  host controller function.  When this constant is set to '1' the host
//  embeded host controller functions are implemented.  When set to '0' this
//  constant will cause most of the gates associated with the embeded host
//  functoin to be removed by your synthesizer.
parameter IMPLEMENT_EMBEDED_HOST = 1'b 1; //  EMBEDDED HOST REMOVE ON
//  EMBEDDED HOST REMOVE OFF
//  EMBEDDED HOST ADD ON  
// CONSTANT IMPLEMENT_EMBEDED_HOST : std_ulogic := '0'; -- implement device only
//  EMBEDDED HOST ADD OFF
//  Add interrupt constant which can be read by software to figure out where the interrupt has been assigned
//  this is useful with ARC reconfigurable processors which can move the interrupt around.
//  For standalone release, we're defining it to be a 1.
//  This value will be read in the ADD_INFO register.
parameter IRQ_NUM = 0; 
//  These two constants control the number of endpoints the up_int will
//  implement.  When set to zero the enpoints won't be implemented.
//  When set to 1 the enpoints will be implemented.
parameter EN_EP_CTL_4_7 = 1'b 1; //  Enables endpoints 4-7
parameter EN_EP_CTL_8_15 = 1'b 1; //  Enables endpoints 8-15
//  This constant is used to enable the DMA controller within the 
//  uProcessor interface to write the entire BDT back to memory.
//  Normally the DMA controller will only write back the first two
//  bytes of the BDT when EN_BDT_4_BYTE_WRITE equals 0. When set to 1 
//  the DMA controller will write back the entire four bytes of the BDT.
parameter EN_BDT_4_BYTE_WRITE = 1'b 0; 
//  FIFO Depths For now we will use a 16 deep fifo for transmit and receive
//  and a 4 byte deep fifo for status. NOTE: The address size must track the
//  depth of the fifo.
// 
//  valid combos
//  DEPTH ADDR
//   16    3
//    8    2
//    4    1
parameter STAT_FIFO_DEPTH = 4; 
parameter STAT_FIFO_ADDR = 1; 
parameter RX_FIFO_DEPTH = 8; 
parameter RX_FIFO_ADDR = 2; 
parameter TX_FIFO_DEPTH = 8; 
parameter TX_FIFO_ADDR = 2; 
//  vusb_xcvr mode control
//  when using the xcvr in differential mode, this signal will be tied to a
//  zero, when the transceiver is single ended mode tie this to a one
parameter VUSB_XCVR_MODE_SINGLE_ENDED = 1'b 0;