vusb_tst.v
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/*******************************************************************************
-- File Type: Verilog HDL
-- Tool Version: VHDL2verilog v4.4 Tue Sep 19 10:06:32 EDT 2000 SunOS 5.5.1
-- Input file was: vusb_tst
-- Date Created: Tue Jul 16 14:00:53 2002
*******************************************************************************/
`timescale 1 ns / 1 ps // timescale for following modules
// ----------------------------------------------------------------------------
// Copyright 2001 VAutomation Inc. Nashua NH USA. All rights reserved.
// This software is provided under license and contains proprietary
// and confidential material which is the property of VAutomation Inc.
// HTTP://www.vautomation.com
// ----------------------------------------------------------------------------
// File Name: $Workfile: vusb_tst.vhdl$
// Revision: $Revision: 1.2 $
// Description:
// vusb_tst module
//
// This module instantiates the test bench that is used for the VUSB 1.1
// design. The test bench is made up of:
//
// vusb_host_ctl - the host controller used to stimulate the VUSB Bus.
// vusb_bias - Performs the function of the pull-up and pull-down
// terminators
// vusb_p11 - Simulates the USB transceiver.
// vusb_tb_clk_gen - Generates USB Clock for DPLL.
//
//
// Created : 2001-05-10 1:15 PM Eastern Daylight Time
// Last update: 2002-04-04
// -----------------------------------------------------------------------------
// This product is licensed to:
// John Princen of RouteFree
// for use at site(s):
// broadon
// -----------Revision History--------------------------------------------------
// $Log:
// 18 VUSB 1.17 7/10/02 7:21:22 PM Will Sanborn Routed
// usb_b_sess_end_n from otg_loopback to host_ctl so it could detect the
// end of OTG testing. Also added comments to problem areas in the
// translation of the host_ctl to verilog.
// 17 VUSB 1.16 6/27/02 2:29:22 PM Will Sanborn Changed
// test bench so two separate clocks are used, one for system and one
// for clk48mhz, before they were both clocked off the 48 MHz clock.
// 16 VUSB 1.15 4/11/02 2:49:08 PM Patrick Koran all
// checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
// 15 VUSB 1.14 11/7/01 9:00:58 AM Tom Frechette Bring in
// vbus sense to turn off dp_high and dm_high. Change the polarity of
// the dp_low and dm_low.
// 14 VUSB 1.13 8/13/01 11:08:06 AM Tom Frechette The Arc
// version was checked in.
// 13 VUSB 1.12 8/7/01 11:21:12 AM Monika Leary Added
// replacement variables for arc
// 12 VUSB 1.11 7/3/01 4:42:08 PM Tom Frechette Changed
// mode to a constant in vusb_cfg.
// 11 VUSB 1.10 6/28/01 9:28:20 AM Tom Frechette Made
// dplus & dminus inouts on vusb_bias.
// 10 VUSB 1.9 6/27/01 4:59:57 PM Tom Frechette Changed
// component instance for p11
// 9 VUSB 1.8 6/22/01 1:19:03 PM Monika Leary Changed
// vusbtst to vusb_tst and vusbp11 to vusb_p11
// 8 VUSB 1.7 6/22/01 1:13:55 PM Monika Leary
// 7 VUSB 1.6 6/22/01 12:09:07 PM Monika Leary Removed
// usb_mode assignment
// 6 VUSB 1.5 6/22/01 9:35:33 AM Tom Frechette Changed
// of clk_gen
// 5 VUSB 1.4 6/22/01 9:11:11 AM Tom Frechette Changed
// name of config package
// 4 VUSB 1.3 6/21/01 4:43:58 PM Monika Leary Made
// usb_mode an input
// 3 VUSB 1.2 6/21/01 10:42:54 AM Tom Frechette Added
// comments.
// 2 VUSB 1.1 6/15/01 3:28:35 PM Tom Frechette Changed
// name to rst48
// 1 VUSB 1.0 6/15/01 2:31:06 PM Tom Frechette
// $
// $NoKeywords$
// -----------------------------------------------------------------------------
// ------------------------------------------------------------------------------
// Copyright 1995 VAutomation Inc. Nashua NH (603)882-2282 ALL RIGHTS RESERVED.
// This software is provided under license and contains proprietary and
// confidential material which is the property of VAutomation Inc.
//
// File: vusb_cfg.vhd USB Configuration file.
//
// Revision: $Revision: 1.2 $
//
// Description: A Package file for the usb core that defines global usb constants
// that contol how the VUSB core is synthesised.
//
// ---------------------------------------------------------------------------
// This product is licensed to:
// $name$ of $company$
// for use at site(s):
// $site$
// ------------------------------------------------------------------------------
// Revision History
// $Log:
// 32 VUSB 1.31 7/5/02 9:15:50 AM Chris Kolb Moved
// VUSB build configruation Revision constant to vusb_cfg, and updated
// the rev number to 3.0.
// 31 VUSB 1.30 4/11/02 2:49:09 PM Patrick Koran all
// checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
// 30 VUSB 1.29 3/18/02 10:52:11 AM Tom Frechette Changed
// IRQ_NUM default to 0x0.
// 29 VUSB 1.28 3/15/02 2:39:08 PM Tom Frechette Added
// Interupt info into add_info register.
// 28 VUSB 1.27 2/7/02 4:49:00 PM Tom Frechette Removed
// sync config variable.
// 27 VUSB 1.26 8/23/01 9:48:58 AM Tom Frechette
// 26 VUSB 1.25 7/25/01 3:41:35 PM Tom Frechette Changed
// FIFO Parameter Names.
// 25 VUSB 1.24 7/10/01 3:03:41 PM Tom Frechette Moved
// HOST comment for verilog.
// 24 VUSB 1.23 7/6/01 7:44:00 AM Tom Frechette Added
// host comments around host constant to make it look like vusb_sie.
// 23 VUSB 1.22 7/6/01 7:34:33 AM Tom Frechette Added
// device constant comment for ARC.
// 22 VUSB 1.21 7/3/01 4:42:08 PM Tom Frechette Changed
// mode to a constant in vusb_cfg.
// 21 VUSB 1.20 6/22/01 3:09:48 PM Tom Frechette Changed
// endpoint number.
// 20 VUSB 1.19 6/21/01 9:59:56 AM Tom Frechette Changed
// the name and added fifo constants
// 19 VUSB 1.18 6/21/01 9:51:24 AM Tom Frechette
// 18 VUSB 1.17 5/25/01 10:25:08 AM Monika Leary Set
// synchronous reset constant to '1'
// 17 VUSB 1.16 5/17/01 2:52:48 PM Monika Leary Added
// USE_SYNC_RESET constant
// 16 VUSB 1.15 12/14/00 8:42:11 AM Christopher Meyers RCS
// Keyword To StarTeam Keyword Translation
// 15 VUSB 1.14 12/13/00 7:58:39 PM Chris Kolb Removed
// the HOST_WITHOUT_HUB constant. This control is now a Endpt0 control
// register bit in up_int.vhd.
// 14 VUSB 1.13 12/13/00 7:58:31 PM Gregory Recupero Removed
// ^M's
// 13 VUSB 1.12 12/13/00 7:58:26 PM Mark Pettigrew
// ulogicified source - no functional changes
// 12 VUSB 1.11 12/13/00 7:58:19 PM Chris Kolb Change
// type of HOST_WITHOUT_HUB from std_logic to integer so that it could
// be used to initialize a _synopsysTM(TM) compatible generic.
// 11 VUSB 1.10 12/13/00 7:58:14 PM Chris Kolb Set
// constant to support Host to Low Speed device thru a hub.
// 10 VUSB 1.9 12/13/00 7:58:07 PM Chris Kolb Changed
// LOW_SPEED_DEV constant to type integer to support generics.
// 9 VUSB 1.8 12/13/00 7:57:58 PM Christopher Meyers
// removed ASIC_IMPLEMENTATION constant
// 8 VUSB 1.7 12/13/00 7:57:46 PM Chris Kolb Remove
// ^M's. No functional changes.
// 7 VUSB 1.6 12/13/00 7:57:39 PM Chris Kolb Added
// HOST_WITHOUT_HUB constant to support new code in the DPLLNRZI.
// 6 VUSB 1.5 12/13/00 7:57:19 PM Chris Kolb Turned
// host mode back on.
// 5 VUSB 1.4 12/13/00 7:57:12 PM Chris Kolb Reverted
// to device only implementation.
// 4 VUSB 1.3 12/13/00 7:57:08 PM Chris Kolb Added
// revision string.
// 3 VUSB 1.2 12/13/00 7:57:03 PM Chris Kolb Enabled
// implementation of embedded host functions.
// 2 VUSB 1.1 12/13/00 7:56:58 PM Chris Kolb Added
// IMPLEMENT_EMBEDED_HOST constant.
// 1 VUSB 1.0 12/13/00 7:56:51 PM Chris Kolb initial
// revision
// $
//
//
// ------------------------------------------------------------------------------
module vusb_tst (usb_clk,
usb_rst_a,
usb_clk48,
usb_rst48_a,
usb_rcv,
usb_dp,
usb_dm,
usb_dpo,
usb_dmo,
usb_oe_n,
usb_speed,
usb_suspnd,
usb_dp_high,
usb_dp_low_n,
usb_dm_high,
usb_dm_low_n,
usb_id,
usb_sess_vld_n,
usb_a_vbus_vld_n,
usb_b_sess_end_n,
usb_vbus_on_n,
usb_vbus_chg_n,
usb_vbus_dschg_n);
// file containing translation of VHDL package 'vusb_cfg'
output usb_clk;
output usb_rst_a;
output usb_clk48;
output usb_rst48_a;
output usb_rcv;
output usb_dp;
output usb_dm;
`include "vusb_cfg.v"
input usb_dpo;
input usb_dmo;
input usb_oe_n;
input usb_speed;
input usb_suspnd;
input usb_dp_high;
input usb_dp_low_n;
input usb_dm_high;
input usb_dm_low_n;
output usb_id; // id pin from mini connectors
output usb_sess_vld_n; // "A" session valid
output usb_a_vbus_vld_n; // "A" VBUS valid
output usb_b_sess_end_n; // "B" session end
input usb_vbus_on_n; // turn on vbus
input usb_vbus_chg_n; // charge vbus
input usb_vbus_dschg_n;
wire usb_clk;
wire usb_rst_a;
wire usb_clk48;
wire usb_rst48_a;
wire usb_rcv;
wire usb_dp;
wire usb_dm;
wire usb_id;
wire usb_sess_vld_n;
wire usb_a_vbus_vld_n;
wire usb_b_sess_end_n;
wire usb_b_sess_end_n_l;
wire usb_dplus;
wire usb_dminus;
wire usb_dmo_i;
wire [16:1] usb_speed_dp;
wire [16:1] usb_power_dp;
wire tb_is_device;
wire gnd;
wire vdd;
// ---------------------------------------------------------------------------
// default assignments
// ---------------------------------------------------------------------------
assign gnd = 1'b 0;
assign vdd = 1'b 1;
assign usb_speed_dp = {16{1'b 0}};
assign usb_power_dp = {16{1'b 0}};
assign usb_b_sess_end_n = usb_b_sess_end_n_l;
// ---------------------------------------------------------------------------
// component connections
// ---------------------------------------------------------------------------
defparam
u_host_ctl.lsdev = LOW_SPEED_DEV;
vusb_host_ctl u_host_ctl (.dplus(usb_dplus),
.dminus(usb_dminus),
.port_sel(),
.low_speed_dp(),
.connect_dp(),
.rmt_wake_dp(),
.speed_dp(usb_speed_dp),
.power_dp(usb_power_dp),
.usb_b_sess_end_n(usb_b_sess_end_n_l),
.tb_is_device(tb_is_device),
.sim_done());
vusb_bias u_vusb_bias (.usb_dp_high(usb_dp_high),
.usb_dp_low_n(usb_dp_low_n),
.usb_dm_high(usb_dm_high),
.usb_dm_low_n(usb_dm_low_n),
.tb_is_device(tb_is_device),
.dplus(usb_dplus),
.dminus(usb_dminus));
`ifdef BB // For BBSoc we use NEC xcvr
wire usbxr_y1, usbxr_fl, usb_oen, usb_ien, usbxr_ose;
wire t_dp, t_dm;
usb_ioblk usb_ioblk(
.usb_suspnd(gnd),
.usbxr_y1(usbxr_y1),
.usb_oe_n(usb_oe_n),
.usb_dpo(usb_dpo),
.usb_dmo(usb_dmo),
.usb_speed(usb_speed),
.usbxr_oen(usb_oen),
.usbxr_ien(usb_ien),
.usbxr_fl(usbxr_fl),
.usbxr_ose(usbxr_ose),
.usb_rcv(usb_rcv));
usb_xcvr usb_xcvr(
.usb_dpo(usb_dpo),
.usbxr_ose(usbxr_ose),
.usbxr_oen(usb_oen),
.usbxr_ien(usb_ien),
.usbxr_fl(usbxr_fl),
.usbxr_y1(usbxr_y1),
.usb_dp(usb_dp),
.usb_dm(usb_dm),
.dp_o(t_dp),
.dm_o(t_dm));
usb_hostio usb_hostio (
.t_p(t_dp),
.t_m(t_dm),
.w_p(usb_dplus),
.w_m(usb_dminus),
.oe(usb_oen)
);
`else
vusb_p11 u_vusb_p11 (.oe_n(usb_oe_n),
.rcv(usb_rcv),
.vp(usb_dp),
.vm(usb_dm),
.suspnd(gnd),
.speed(usb_speed),
.dminus(usb_dminus),
.dplus(usb_dplus),
.vpo(usb_dpo),
.vmo(usb_dmo),
.gnds(gnd),
.pwr(vdd));
`endif
assign usb_dmo_i = VUSB_XCVR_MODE_SINGLE_ENDED === 1'b 1 ? ~(usb_dpo | usb_dmo) :
usb_dmo; // When usb_xcvr_mode_single_ended = '1' usb_dmo is actually se0
vusb_tb_clk_gen u_clk_gen (.rst_a(usb_rst_a),
.rst(),
.clk(usb_clk),
.rst48_a(usb_rst48_a),
.rst48(),
.clk_48mhz(usb_clk48));
vusb_otg_lpbck u_vusb_otg_lpbck (.usb_id(usb_id),
.usb_sess_vld_n(usb_sess_vld_n),
.usb_a_vbus_vld_n(usb_a_vbus_vld_n),
.usb_b_sess_end_n(usb_b_sess_end_n_l),
.usb_vbus_on_n(usb_vbus_on_n),
.usb_vbus_chg_n(usb_vbus_chg_n),
.usb_vbus_dschg_n(usb_vbus_dschg_n));
// ---------------------------------------------------------------------------
// component instantiations
// ---------------------------------------------------------------------------
endmodule // module vusb_tst