// VERSION:1.00 DATE:00/11/27 OPENCAD Verilog Library
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDIPAST2R ( H01 );
    input H01;

    buf ( _H01, H01 );

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine