// VERSION:1.00 DATE:00/09/20 OPENCAD Verilog Library
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDSECGNDX2U ( N01 );
    output N01;

    buf ( N01, 1'b0 );

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine