TBADHAY0.v
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// VERSION:4.00 DATE:2001/05/14 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TBADHAY0 ( N01 , N02 , H01 , H02 ) ;
input H01 ;
input H02 ;
output N01 ;
output N02 ;
buf ( _H01 , H01 ) ;
buf ( _H02 , H02 ) ;
xor ( N01 , _H01 , _H02 ) ;
and ( N02 , _H01 , _H02 ) ;
specify
specparam DMY_SPC=1;
( H01 *> N02 ) = ( DMY_SPC,
DMY_SPC );
( H02 *> N02 ) = ( DMY_SPC,
DMY_SPC );
if ( H01 )
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H01 )
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H02 )
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H02 )
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine