// VERSION:4.00 DATE:2001/05/14 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
// generated by sldtoveri Version 1.3.4
// Tue Nov  7 20:37:01 1995

module TBINVX10RE ( N01 , H01 ) ;
 input H01 ;
 output N01 ;

  buf  	 ( _H01 , H01 ) ;
  not  	 ( N01 , _H01 ) ;

 specify
        specparam DMY_SPC=1;

// path from H01 to N01
  ( H01 *>  N01 ) = ( DMY_SPC,
                      DMY_SPC );
 endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine