AAD3835BM.v
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// AAD3835BM.v v1 Frank Berndt
// stub for NEC triple video DAC;
// :set tabstop=4
`timescale 1ns/1ns
module AAD3835BM (
ATBO0, ATBO1, ATBO2, ATBO3, ATBO4, ATBO5, ATBO6, ATBO7,
ATBO8, ATBO9, VOA, VOB, VOC, AGND1, AGND2, AGND3, AVDD1, AVDD2, AVDD3,
BUNRI, CLKA, CLKB, CLKC, DA0, DA1, DA2, DA3, DA4, DA5, DA6, DA7, DB0, DB1,
DB2, DB3, DB4, DB5, DB6, DB7, DC0, DC1, DC2, DC3, DC4, DC5, DC6, DC7, MODE1,
MODE2, PDB, TBI0, TBI1, TBI2, TBI3, TBI4, TBI5, TBI6, TBI7, TBI8, TBI9, TEST
);
output ATBO0, ATBO1, ATBO2, ATBO3, ATBO4, ATBO5, ATBO6, ATBO7, ATBO8, ATBO9,
VOA, VOB, VOC;
input AGND1, AGND2, AGND3, AVDD1, AVDD2, AVDD3, BUNRI, CLKA, CLKB, CLKC, DA0,
DA1, DA2, DA3, DA4, DA5, DA6, DA7, DB0, DB1, DB2, DB3, DB4, DB5, DB6,
DB7, DC0, DC1, DC2, DC3, DC4, DC5, DC6, DC7, MODE1, MODE2, PDB, TBI0,
TBI1, TBI2, TBI3, TBI4, TBI5, TBI6, TBI7, TBI8, TBI9, TEST;
// input CLKA; // dac A clock;
// input CLKB; // dac B clock;
// input CLKC; // dac C clock;
wire [7:0] DA = {DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0}; // dac A digital input data;
wire [7:0] DB = {DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0}; // dac B digital input data;
wire [7:0] DC = {DC7, DC6, DC5, DC4, DC3, DC2, DC1, DC0}; // dac C digital input data;
// output VOA; // analog A video output;
// output VOB; // analog B video output;
// output VOC; // analog C video output;
// input PDB; // power-down input, 0=down 1=normal;
// input BUNRI; // test mode;
// input TEST; // test mode;
// input MODE1; // test mode;
// input MODE2; // test mode;
// test bus inputs;
wire [9:0] TBI = {TBI9, TBI8, TBI7, TBI6, TBI5, TBI4, TBI3, TBI2, TBI1, TBI0};
// test bus outputs;
wire [9:0] ATBO = {ATBO9, ATBO8, ATBO7, ATBO6, ATBO5, ATBO4, ATBO3, ATBO2, ATBO1, ATBO0};
reg dac_mon;
reg [1:256*8] filename;
integer file;
integer ret;
// warn about stub;
initial
begin
$display("%M: behavioral stub");
`ifdef NEC_TEST_VECTORS
`else
dac_mon = $getstr$plusarg("dac_mon=", filename);
`endif
file = $fopen(filename);
$fdisplay(file, "// DAC outputs\n Luma Chroma Composite\n");
$fflush(file);
end
// clock inputs into registers;
// so they don't get optimized out;
reg [7:0] dac_a;
reg [7:0] dac_b;
reg [7:0] dac_c;
// Use CLKA for everything, since it should be the same as
// other clocks
always @(posedge CLKA)
begin
dac_a <= DA;
if (dac_mon)
begin
$fdisplay(file, "%d %d %d", dac_c, dac_a, dac_b);
$fflush(file);
end
end
always @(posedge CLKB)
begin
dac_b <= DB;
end
always @(posedge CLKC)
begin
dac_c <= DC;
end
// report mode changes;
always @(BUNRI or TEST or MODE1 or MODE2)
begin
$display("%t: %M: mode change, BUNRI %b, TEST %b, MODE1 %B, MODE2 %B",
$time, BUNRI, TEST, MODE1, MODE2);
end
always @(PDB)
$display("%t: %M: power down %b", $time, PDB);
// drive outputs with Xs;
assign VOA = 'bx;
assign VOB = 'bx;
assign VOC = 'bx;
assign ATBO = 'bx;
endmodule