`timescale 1ns/1ns

module GCB_DFF (q, qn, d, cp, sdn, cdn);
   input d, cp, sdn, cdn;
   output q, qn;
   reg tq;

   assign #1 qn = (!sdn && !cdn) ? 1'b0 : ~tq;
   assign #1 q  = tq;

   always @ (posedge cp or negedge cdn or negedge sdn) begin
      if (sdn && cdn)
         tq = d;
      else if (!sdn && cdn)
         tq = 1'b1;
      else
         tq = 1'b0;
   end

endmodule