// ri.v v1 Frank Berndt
// initial behavioral memory interface;
// :set tabstop=4

module ri_model (
	sysclk, memclk, reset_l,
	cbus_read_enable, cbus_write_enable,
	cbus_command, cbus_data,
	cbus_read_request, cbus_read_grant,
	dbus_data, ebus_data,
	dma_ready,
	mi_dma_start, mi_dma_last,
	sp_dma_start, sp_dma_last,
	span_dma_start, span_dma_last,
	pi_dma_start, pi_dma_last,
	si_dma_start, si_dma_last,
	ai_dma_start, ai_dma_last,
	vi_dma_start, vi_dma_last,
	mi_dbus_read_enable, mi_dbus_write_enable,
	sp_dbus_read_enable, sp_dbus_write_enable,
	span_dbus_read_enable, span_dbus_write_enable,
	pi_dbus_write_enable,
	si_dbus_write_enable,
	mcke, maddr, mbank,
	mdin, mdin_ena, mdout, mdout_ena,
	mcs, mras, mcas, mwe, mdqm
);

`include "rcp.vh"

	// global signals;
	// sysclk and memclk are rising edge aligned;
	// reset_l is synchronous to memclk, active 64 for memclk;

	input sysclk;			// system clock;
	input memclk;			// memory clock;
	input reset_l;			// system reset;

	// cbus interface;

	input cbus_read_enable;
	input cbus_write_enable;
	input [2:0] cbus_command;
	inout [31:0] cbus_data;
	output cbus_read_request;
	input cbus_read_grant;

	// dbus, ebus;

	inout [DBUS_DATA_SIZE-1:0] dbus_data;
	inout [EBUS_DATA_SIZE-1:0] ebus_data;

	output dma_ready;
	output mi_dma_start, mi_dma_last;
	output sp_dma_start, sp_dma_last;
	output span_dma_start, span_dma_last;
	output pi_dma_start, pi_dma_last;
	output si_dma_start, si_dma_last;
	output ai_dma_start, ai_dma_last;
	output vi_dma_start, vi_dma_last;

	// device controls;

	output mi_dbus_read_enable;
	output mi_dbus_write_enable;
	output sp_dbus_read_enable;
	output sp_dbus_write_enable;
	output span_dbus_read_enable;
	output span_dbus_write_enable;
	output pi_dbus_write_enable;
	output si_dbus_write_enable;

	// memory interface;
	// the registered io cells are in the pad layer;

	output [1:0] mcke;			// clock enables;
	output [13:0] maddr;		// row/col address;
	output [1:0] mbank;			// bank address;
	input [63:0] mdin;			// input data;
	output [7:0] mdin_ena;		// input register enables;
	output [63:0] mdout;		// output data;
	output [7:0] mdout_ena;		// output enables;
	output [1:0] mcs;			// chip selects;
	output mras, mcas, mwe;		// command;
	output [7:0] mdqm;			// byte enables;

	// internal variables;

	parameter MEM_SIZE = (16*1024*1024);

	// logic;

	reg ri_mon;				// ri monitor flag;

	initial
	begin
		$display("%M: behavioral model: %0dMB (x64 space)", MEM_SIZE >> 20);
		ri_mon = $test$plusargs("ri_mon");
	end

parameter
	STATE_CBUS_IDLE = 0,
	STATE_CBUS_WRITE_LENGTH = 1,
	STATE_CBUS_READ_RI = 2,
	STATE_CBUS_WRITE_RI = 3;

	// main memory;
	// limit in size to reduce simulator size;

	reg [63:0] mem [(MEM_SIZE/8)-1:0];

	// cbus interface block;

	reg [2:0] cbus_cmd_reg;
	reg [31:0] cbus_data_reg;
	wire [31:0] cbus_data_out;
	reg [63:0] dbus_in;
	reg [63:0] dbus_out;
	reg [7:0] ebus_in;
	reg [7:0] ebus_out;
	wire [7:0] ebus_ext;
	wire ri_dbus_read_enable;
	wire ri_dbus_write_enable;
	wire ri_ebus_gen;

	// devices for which we generate ebus bits;
	// mi ebus generation moved to ri because mi ebus test mode is gone;

	assign ri_ebus_gen = mi_dbus_write_enable | sp_dbus_write_enable
		| pi_dbus_write_enable | si_dbus_write_enable;

	// extend 16-bit word bits 0;

	assign ebus_ext = {
		dbus_data[48],dbus_data[48],
		dbus_data[32],dbus_data[32],
		dbus_data[16],dbus_data[16],
		dbus_data[0],dbus_data[0] };

	always @(posedge sysclk)
	begin
		cbus_cmd_reg <= cbus_command;
		cbus_data_reg <= cbus_read_enable? cbus_data : cbus_data_out;
		if(ri_dbus_read_enable) begin
			dbus_in <= dbus_data;
			ebus_in <= ri_ebus_gen? ebus_ext : ebus_data;
		end
	end

	// bus drivers;

	assign cbus_data = cbus_write_enable? cbus_data_reg : 32'bz;
	assign dbus_data = ri_dbus_write_enable? dbus_out : 64'bz;
	assign ebus_data = ri_dbus_write_enable? ebus_out : 8'bz;

	// decode ri register access;
	// ri responds to entire ri register space;

	wire ri_regsel;

	assign ri_regsel = reset_l & ((cbus_data_reg & BUS_ADDRESS_MASK) == BUS_ADDRESS_RI);

	// cbus state machine;

	reg dma_ready;
	reg dma_start;
	reg cbus_read_request;
	reg next_read_request;
	reg [2:0] cbus_state;				// cbus state;
	reg [31:0] reg_addr;				// register address;
	reg [31:0] mem_addr;				// dma byte address;
	reg dma_x36;						// dma to x36 space;
	reg [31:0] dma_addr;				// dma word address;
	reg [7:0] dma_mask, dma_lmask;		// first & last data masks;
	reg [3:0] dbus_rdev, dbus_wdev;
	reg [3:0] dma_dev;
	reg next_dma_req;
	reg [7:0] dma_req;
	reg dma_subblk, dma_masked, dma_down, dma_nseq, dma_read;
	reg [7:0] dma_len;
	reg [3:0] dma_nword, dma_cnt;
	reg [2:0] dma_lat;					// initial latency to dma_start;
	reg [3:0] dma_delay;				// delay from dma_start to dbus data;

	// return lower cbus address as reg read data;

	assign cbus_data_out = {reg_addr[15:0], reg_addr[15:0]};

	always @(posedge sysclk)
	begin
		if(!reset_l) begin
			cbus_state <= STATE_CBUS_IDLE;
			dma_ready <= 1;
			cbus_read_request <= 0;
			reg_addr <= 'bx;
			mem_addr <= 'bx;
			dma_x36 <= 'bx;
			dma_addr <= 'bx;
			dma_mask <= 'bx;
			dma_lmask <= 'bx;
			dbus_rdev <= 'bx;
			dbus_wdev <= `CBUS_DEV_RI;
			dma_dev <= 'bx;
			dma_req <= 'h00;
			dma_subblk <= 'bx;
			dma_masked <= 'bx;
			dma_down <= 'bx;
			dma_nseq <= 'bx;
			dma_read <= 'bx;
			dma_len <= 'bx;
			dma_nword <= 'bx;
			dma_cnt <= 'bx;
			dma_lat <= 'b000;
			dma_delay <= 'hx;
	
		end else begin

			next_read_request = 0;
			next_dma_req = 0;

			if(cbus_command == `CBUS_CMD_DMA)
				dma_ready = 0;

			case(cbus_state)
				STATE_CBUS_IDLE: begin
					case(cbus_cmd_reg)
						// dma request;

						`CBUS_CMD_DMA: begin
							mem_addr <= cbus_data_reg;
							cbus_state <= STATE_CBUS_WRITE_LENGTH;
						end

						// register write command;

						`CBUS_CMD_WRITE : begin
							if(ri_regsel) begin
								reg_addr <= cbus_data_reg;
								cbus_state <= STATE_CBUS_WRITE_RI;
							end else
								cbus_state <= STATE_CBUS_IDLE;
						end

						// register read command;

						`CBUS_CMD_READ : begin
							if(ri_regsel) begin
								next_read_request = 1;
								reg_addr <= cbus_data_reg;
								cbus_state <= STATE_CBUS_READ_RI;
							end else
								cbus_state <= STATE_CBUS_IDLE;
						end

						default :
							cbus_state <= STATE_CBUS_IDLE;
					endcase
				end

				STATE_CBUS_WRITE_LENGTH: begin : cbus_write
					reg subblk, masked, down, nseq, read;
					reg [3:0] dev;
					reg [7:0] delay;
					reg [6:0] cnt;
					reg [7:0] len;
					reg [3:0] nword;
					reg [7:0] mask, lmask;
					integer msize;
					reg x36;
					reg [31:0] addr;
					reg dodma;

					dodma = 1;
					{subblk,masked,down,nseq,dev,delay,read,cnt} = cbus_data_reg;
					nword = cnt[6:3];
					mask = 8'hff >> mem_addr[2:0];		// first word byte mask;
					lmask = 8'hff << (7 - cnt[2:0]);	// last word byte mask;
					len = (cnt + 1) - mem_addr[2:0];	// intended length;

					if(ri_mon) begin
						$display("%t: ri: dma subblk %b, masked %b, down %b, nseq %b, dev %0d, delay %0d, read %b, cnt 0x%h (%0d)",
							$time, subblk, masked, down, nseq, dev, delay, read, cnt, len);
					end
					addr = mem_addr;
					msize = MEM_SIZE;
					x36 = (addr[31:24] == 8'h00);
					if(x36)
						msize = msize >> 1;
					if(addr[31])
						addr[31] = 0;
					else if( !x36)
						addr[31:24] = addr[31:24] - 1;
					if((addr >= msize) || ((addr + len) >= msize)) begin
						$display("ERROR: %t: ri: outside memory, 0x%x len %0d", $time, mem_addr, len);
						dodma = 0;
					end
					if(subblk & (~read | down)) begin
						$display("ERROR: %t: ri: illegal subblk on write/down", $time);
						dodma = 0;
					end
					if((delay[7:4] != 'h0) & (delay[7:4] != 'hf)) begin
						$display("ERROR: %t: ri: delay outside bounds 0x%h", $time, delay);
						dodma = 0;
					end
					if(masked & read) begin
						$display("ERROR: %t: ri: masked read is illegal", $time);
						dodma = 0;
					end
					if(masked & (nword >= 8)) begin
						$display("ERROR: %t: ri: length %0d too large for masked write", $time, len);
						dodma = 0;
					end

					delay = delay - 2;
					if(read) begin
						dbus_rdev <= dev;
						dbus_wdev <= `CBUS_DEV_RI;
					end else begin
						dbus_rdev <= `CBUS_DEV_RI;
						dbus_wdev <= dev;
					end

					// setup dma state;

					next_dma_req = dodma;
					dma_dev <= dev;
					dma_x36 = x36;
					dma_addr <= addr >> 3;
					dma_mask <= mask;
					dma_lmask <= lmask;
					dma_subblk <= subblk;
					dma_masked <= masked;
					dma_down <= down;
					dma_nseq <= nseq;
					dma_read <= read;
					dma_len <= len;
					dma_nword <= nword + masked;
					dma_delay <= 0 - delay[3:0];
					dma_cnt <= 0;
					dma_lat <= $random & 3'b011;
					cbus_state <= STATE_CBUS_IDLE;
				end

				// read ri register;

				STATE_CBUS_READ_RI: begin
					if(ri_mon & cbus_read_grant)
						$display("%t: ri: read reg 0x%h data 0x%h", $time, reg_addr, cbus_data_out);
					if(cbus_read_grant)
						cbus_state <= STATE_CBUS_IDLE;
					else
						next_read_request = 1;
				end

				// write ri register;

				STATE_CBUS_WRITE_RI: begin
					if(ri_mon)
						$display("%t: ri: write reg 0x%h data 0x%h", $time, reg_addr, cbus_data_reg);
					cbus_state <= STATE_CBUS_IDLE;
				end

				default: begin
					cbus_state <= 'bx;
					$display("%t: ri: illegal cbus state", $time);
				end
			endcase

			cbus_read_request <= next_read_request;
			dma_req <= {8{~dma_start}} & {dma_req[6:0],next_dma_req};
		end
	end

	// decode dbus read enables;

	assign ri_dbus_read_enable = (dbus_rdev == `CBUS_DEV_RI);
	assign mi_dbus_read_enable = (dbus_rdev == `CBUS_DEV_MI);
	assign sp_dbus_read_enable = ((dbus_rdev == `CBUS_DEV_SP) | (dbus_rdev == `CBUS_DEV_CMD));
	assign span_dbus_read_enable = (dbus_rdev == `CBUS_DEV_SPAN);

	// decode dbus write enables;
	// CBUS_DEV_CMD does not do writes;

	assign ri_dbus_write_enable = (dbus_wdev == `CBUS_DEV_RI);
	assign mi_dbus_write_enable = (dbus_wdev == `CBUS_DEV_MI);
	assign sp_dbus_write_enable = (dbus_wdev == `CBUS_DEV_SP);
	assign span_dbus_write_enable = (dbus_wdev == `CBUS_DEV_SPAN);
	assign pi_dbus_write_enable = (dbus_wdev == `CBUS_DEV_PI);
	assign si_dbus_write_enable = (dbus_wdev == `CBUS_DEV_SI);

	// dbus state machine;
	// delay dbus data phase to approximate worst bb latency;

	reg mi_dma_start, mi_dma_last;
	reg sp_dma_start, sp_dma_last;
	reg span_dma_start, span_dma_last;
	reg pi_dma_start, pi_dma_last;
	reg si_dma_start, si_dma_last;
	reg ai_dma_start, ai_dma_last;
	reg vi_dma_start, vi_dma_last;
	reg dma_last;
	reg dma_burst;
	reg [7:0] dbus_start, dbus_pipe, dbus_last;

	always @(posedge sysclk)
	begin
		if(!reset_l) begin
			dma_start <= 0;
			mi_dma_start <= 0;
			sp_dma_start <= 0;
			span_dma_start <= 0;
			pi_dma_start <= 0;
			si_dma_start <= 0;
			ai_dma_start <= 0;
			vi_dma_start <= 0;
			dma_last <= 0;
			dma_burst <= 0;
			dbus_start <= 'h00;
			dbus_pipe <= 'h00;
			dbus_last <= 'h00;
		end else begin : dbus_fsm
			reg start, last, burst;
			reg do_mask, do_data, do_last;
			reg [31:0] addr;
			reg [63:0] data, rdata, mdata, wmask;
			reg [7:0] dext, rdext;
			reg [7:0] mask;

			// start/last sequencer;

			start = dma_req[dma_lat];
			last = 0;
			burst = start | dma_burst;
			if(burst) begin
				if(dma_nword == 0) begin
					last = 1;
					burst = 0;
				end else
					dma_nword <= dma_nword - 1;
			end
			if(ri_mon & start)
				$display("%t: ri: dbus latency %0d", $time, dma_lat);

			dma_start <= start;
			mi_dma_start <= start & (dma_dev == `CBUS_DEV_MI);
			sp_dma_start <= start & ((dma_dev == `CBUS_DEV_SP) | (dma_dev == `CBUS_DEV_CMD));
			span_dma_start <= start & (dma_dev == `CBUS_DEV_SPAN);
			pi_dma_start <= start & (dma_dev == `CBUS_DEV_PI);
			si_dma_start <= start & (dma_dev == `CBUS_DEV_SI);
			ai_dma_start <= start & (dma_dev == `CBUS_DEV_AI);
			vi_dma_start <= start & (dma_dev == `CBUS_DEV_VI);
			dma_last <= last;
			mi_dma_last <= last & (dma_dev == `CBUS_DEV_MI);
			sp_dma_last <= last & ((dma_dev == `CBUS_DEV_SP) | (dma_dev == `CBUS_DEV_CMD));
			span_dma_last <= last & (dma_dev == `CBUS_DEV_SPAN);
			pi_dma_last <= last & (dma_dev == `CBUS_DEV_PI);
			si_dma_last <= last & (dma_dev == `CBUS_DEV_SI);
			ai_dma_last <= last & (dma_dev == `CBUS_DEV_AI);
			vi_dma_last <= last & (dma_dev == `CBUS_DEV_VI);
			dma_burst <= burst;

			// kick the data pipe after dma_delay clocks;

			dbus_start = {dbus_start[6:0],start};
			dbus_pipe = {dbus_pipe[6:0],start | burst | last};
			dbus_last = {dbus_last[6:0],last};

			// mask, data and last controls;

			do_mask = dma_masked & dbus_start[dma_delay];
			do_data = ~do_mask & dbus_pipe[dma_delay];
			do_last = dbus_last[dma_delay];

			// re-enable arbiter after last data word;

			if(do_last)
				dma_ready <= 1;

			data = {64{1'bx}};
			dext = 8'bx;

			// latch write mask;

			if(do_mask) begin
				wmask = dbus_in;
				if(ri_mon)
					$display("%t: ri: write mask 0x%h", $time, wmask);
			end

			// read/write data;
			// process one doubleword per clock;

			if(do_data) begin
				mask = dma_mask;				// first mask or all 1s;
				if(do_last)
					mask = mask & dma_lmask;	// last mask;
				dma_mask <= 'hff;
				if(dma_masked) begin
					mask[7] = mask[7] & wmask[56];
					mask[6] = mask[6] & wmask[57];
					mask[5] = mask[5] & wmask[58];
					mask[4] = mask[4] & wmask[59];
					mask[3] = mask[3] & wmask[60];
					mask[2] = mask[2] & wmask[61];
					mask[1] = mask[1] & wmask[62];
					mask[0] = mask[0] & wmask[63];
					wmask = wmask << 8;
				end

				// address sequencer;
				// only reads can use sub-block order;

				if(dma_subblk) begin
					addr = dma_addr ^ dma_cnt;
					dma_cnt <= dma_cnt + 1;
				end else begin
					addr = dma_addr;
					dma_addr <= dma_addr + (dma_down? -1 : 1);
				end

				// read/write data;
				// output Xs for non-enabled byte lanes to aid dv;

				if(dma_read) begin
					if(dma_x36) begin
						mdata = mem[addr*2 + 0];
						rdata[63:32] = mdata[63:32];
						rdext[7:4] = { mdata[24], mdata[16], mdata[8], mdata[0] };
						mdata = mem[addr*2 + 1];
						rdata[31:0] = mdata[63:32];
						rdext[3:0] = { mdata[24], mdata[16], mdata[8], mdata[0] };
					end else begin
						rdata = mem[addr];
						rdext = 8'bx;
					end
				end else begin
					rdata = dbus_in;
					rdext = ebus_in;
					if(dma_x36) begin
						mdata = mem[addr*2 + 0];
						data[63:32] = mdata[63:32];
						dext[7:4] = { mdata[24], mdata[16], mdata[8], mdata[0] };
						mdata = mem[addr*2 + 1];
						data[31:0] = mdata[63:32];
						dext[3:0] = { mdata[24], mdata[16], mdata[8], mdata[0] };
					end else begin
						data = mem[addr];
						dext = 8'bx;
					end
				end
				if(mask[7])
					{dext[7],data[63:56]} = {rdext[7],rdata[63:56]};
				if(mask[6])
					{dext[6],data[55:48]} = {rdext[6],rdata[55:48]};
				if(mask[5])
					{dext[5],data[47:40]} = {rdext[5],rdata[47:40]};
				if(mask[4])
					{dext[4],data[39:32]} = {rdext[4],rdata[39:32]};
				if(mask[3])
					{dext[3],data[31:24]} = {rdext[3],rdata[31:24]};
				if(mask[2])
					{dext[2],data[23:16]} = {rdext[2],rdata[23:16]};
				if(mask[1])
					{dext[1],data[15:8]} = {rdext[1],rdata[15:8]};
				if(mask[0])
					{dext[0],data[7:0]} = {rdext[0],rdata[7:0]};

				if( !dma_read) begin
					if(dma_x36) begin
						mem[addr*2 + 0] = { data[63:32],
							7'bx, dext[7], 7'bx, dext[6], 7'bx, dext[5], 7'bx, dext[4] };
						mem[addr*2 + 1] = { data[31:0],
							7'bx, dext[3], 7'bx, dext[2], 7'bx, dext[1], 7'bx, dext[0] };
					end else
						mem[addr] = data;
				end
				if(ri_mon) begin
					$display("%t: ri: %s 0x%h addr 0x%h data 0x%h",
						$time, dma_read? "read" : "write", mask, addr << 3, data);
				end
			end

			// dbus/ebus output;

			{ebus_out,dbus_out} = data;

		end
	end

	// fix DDR outputs;

	assign mcke = 2'b11;
	assign maddr = 'bx;
	assign mbank = 'bx;
	assign mdin_ena = {8{1'b0}};
	assign mdout = {64{1'b0}};
	assign mdout_ena = {8{1'b0}};
	assign mcs = 2'b11;
	assign mras = 'b0;
	assign mcas = 'b0;
	assign mwe = 'b0;
	assign mdqm = {8{1'b0}};

endmodule