vurf.v
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/*
*************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************
*/
// $Id: vurf.v,v 1.1 2002/03/28 00:26:14 berndt Exp $
/*
*************************************************************************
* *
* Project Reality *
* *
* Module: vurf *
* Description: Vector unit custom register file block where *
* the register file is implemented as a 32 word *
* by 128 monolithic structure. *
* *
* which contain address decoding, address *
* transpose logic for load/store addresses, *
* scalar muxing on VT read port and read data *
* registers for all three read ports. *
* *
* This partitioning was decided upon for *
* physical partitioning. *
* *
* This version is for the standard cell *
* implementation of the datapath. *
* *
* Designer: Brian Ferguson *
* Date: 3/30/95 *
* *
*************************************************************************
*/
// vurf.v: RSP vector unit register file
`timescale 1ns / 10ps
module vurf (
preclk_in0,
preclk_in1,
reset_l,
su_instvld_rd,
su_vs_addr_rd,
su_vt_addr_rd,
su_vd_addr_wb,
su_st_rnum_rd,
su_xp_rnum_rd,
su_ld_rnum_wb,
su_sclrdatasl_rd,
su_qrtdatasl_rd,
su_hlfdatasl_rd,
su_whldatasl_rd,
vct_wbv_wr_en_wb,
su_bwe_wb,
su_xposeop_rd,
su_xposeop_wb,
vdp_datatristen_rd,
vdp_rslt_data_wb,
vrf_div_input_rd,
vrf_vs_data_mu,
vrf_vt_data_mu,
su_data_to_from
) ;
input preclk_in0; /* pre-buffered clock for new clocking scheme */
input preclk_in1; /* pre-buffered clock for new clocking scheme */
input reset_l; /* vu active low reset */
input su_instvld_rd; /* valid CP2 instruction for vu */
input [4:0] su_vs_addr_rd; /* register number for vs read */
input [4:0] su_vt_addr_rd; /* decoded register number for vt read */
input [4:0] su_vd_addr_wb; /* register number for datapath writeback */
input [4:0] su_st_rnum_rd; /* register number for stores */
input [4:0] su_xp_rnum_rd; /* register number for xpose stores */
input [4:0] su_ld_rnum_wb; /* register number for load */
input [3:0] su_sclrdatasl_rd; /* selcts for vector, quarter, half or whole scalar data */
input [1:0] su_qrtdatasl_rd; /* selects for scalar quarter data */
input [3:0] su_hlfdatasl_rd; /* selects for scalar half data */
input [7:0] su_whldatasl_rd; /* selects for scalar whole data */
input [7:0] vct_wbv_wr_en_wb; /* short word write enable for datapath results */
input [15:0] su_bwe_wb; /* load port byte write enable */
input su_xposeop_rd; /* transpose op for rd stage (store) */
input su_xposeop_wb; /* transpose op for ac stage (load) */
input vdp_datatristen_rd; /* tristate enable for load/store data bus */
input [127:0] vdp_rslt_data_wb; /* VU computational result from data path */
/*
* The following output signals are data from the register file.
*/
output [15:0] vrf_div_input_rd; /* data for divide unit */
output [127:0] vrf_vs_data_mu; /* read data for vs port */
output [127:0] vrf_vt_data_mu; /* read data for vt port after scalar muxes */
inout [127:0] su_data_to_from; /* data field to/from su */
/*
* reg and wire variables for use within this module.
*/
reg [127:0] vrf_vs_datarg_mu; /* read data for vs port */
reg [127:0] vrf_vt_datarg_mu; /* read data for vt port after scalar muxes */
reg [127:0] vrf_data_from_mu; /* read data for store data port */
reg [7:0] memsl0lo[0:31]; /* register file memory array low byte slice 0 */
reg [7:0] memsl0hi[0:31]; /* register file memory array high bye slice 0 */
reg [7:0] memsl1lo[0:31]; /* register file memory array low byte slice 1 */
reg [7:0] memsl1hi[0:31]; /* register file memory array high bye slice 1 */
reg [7:0] memsl2lo[0:31]; /* register file memory array low byte slice 2 */
reg [7:0] memsl2hi[0:31]; /* register file memory array high bye slice 2 */
reg [7:0] memsl3lo[0:31]; /* register file memory array low byte slice 3 */
reg [7:0] memsl3hi[0:31]; /* register file memory array high bye slice 3 */
reg [7:0] memsl4lo[0:31]; /* register file memory array low byte slice 4 */
reg [7:0] memsl4hi[0:31]; /* register file memory array high bye slice 4 */
reg [7:0] memsl5lo[0:31]; /* register file memory array low byte slice 5 */
reg [7:0] memsl5hi[0:31]; /* register file memory array high bye slice 5 */
reg [7:0] memsl6lo[0:31]; /* register file memory array low byte slice 6 */
reg [7:0] memsl6hi[0:31]; /* register file memory array high bye slice 6 */
reg [7:0] memsl7lo[0:31]; /* register file memory array low byte slice 7 */
reg [7:0] memsl7hi[0:31]; /* register file memory array high bye slice 7 */
reg [127:0] vrf_vt_data_rd; /* read data for vt port after scalar muxes */
reg [15:0] vrf_qrtdata01_rd; /* quarter data for slices 0 and 1 */
reg [15:0] vrf_qrtdata23_rd; /* quarter data for slices 2 and 3 */
reg [15:0] vrf_qrtdata45_rd; /* quarter data for slices 4 and 5 */
reg [15:0] vrf_qrtdata67_rd; /* quarter data for slices 6 and 7 */
reg [15:0] vrf_hlfdata03_rd; /* half data for slices 0,1,2 and 3 */
reg [15:0] vrf_hlfdata47_rd; /* half data for slices 4,5,6 and 7 */
reg [15:0] vrf_whldata_rd; /* whole data for all slices */
reg write_conflict; /* flag warning of two writes to same location */
wire [127:0] vrf_vs_rfout_rd; /* vs read data port of register file */
wire clk; /* vu clock */
assign clk = preclk_in0;
/*
* load write port functionality
*/
wire [4:0] vrf_load_addrsl0_wb; /* register number for write load data slice 0 */
wire [4:0] vrf_load_addrsl1_wb; /* register number for write load data slice 1 */
wire [4:0] vrf_load_addrsl2_wb; /* register number for write load data slice 2 */
wire [4:0] vrf_load_addrsl3_wb; /* register number for write load data slice 3 */
wire [4:0] vrf_load_addrsl4_wb; /* register number for write load data slice 4 */
wire [4:0] vrf_load_addrsl5_wb; /* register number for write load data slice 5 */
wire [4:0] vrf_load_addrsl6_wb; /* register number for write load data slice 6 */
wire [4:0] vrf_load_addrsl7_wb; /* register number for write load data slice 7 */
assign vrf_load_addrsl0_wb = su_ld_rnum_wb ;
assign vrf_load_addrsl1_wb = !su_xposeop_wb ? su_ld_rnum_wb
: { su_ld_rnum_wb[4:3],
(su_ld_rnum_wb[2:0] + 3'h1)&3'h7
} ;
assign vrf_load_addrsl2_wb = !su_xposeop_wb ? su_ld_rnum_wb
: { su_ld_rnum_wb[4:3],
(su_ld_rnum_wb[2:0] + 3'h2)&3'h7
} ;
assign vrf_load_addrsl3_wb = !su_xposeop_wb ? su_ld_rnum_wb
: { su_ld_rnum_wb[4:3],
(su_ld_rnum_wb[2:0] + 3'h3)&3'h7
} ;
assign vrf_load_addrsl4_wb = !su_xposeop_wb ? su_ld_rnum_wb
: { su_ld_rnum_wb[4:3],
(su_ld_rnum_wb[2:0] + 3'h4)&3'h7
} ;
assign vrf_load_addrsl5_wb = !su_xposeop_wb ? su_ld_rnum_wb
: { su_ld_rnum_wb[4:3],
(su_ld_rnum_wb[2:0] + 3'h5)&3'h7
} ;
assign vrf_load_addrsl6_wb = !su_xposeop_wb ? su_ld_rnum_wb
: { su_ld_rnum_wb[4:3],
(su_ld_rnum_wb[2:0] + 3'h6)&3'h7
} ;
assign vrf_load_addrsl7_wb = !su_xposeop_wb ? su_ld_rnum_wb
: { su_ld_rnum_wb[4:3],
(su_ld_rnum_wb[2:0] + 3'h7)&3'h7
} ;
// always @(su_bwe_wb or su_data_to_from or
// vrf_load_addrsl0_wb or vrf_load_addrsl1_wb or
// vrf_load_addrsl2_wb or vrf_load_addrsl3_wb or
// vrf_load_addrsl4_wb or vrf_load_addrsl5_wb or
// vrf_load_addrsl6_wb or vrf_load_addrsl7_wb
// )
always @(negedge clk)
begin
if (su_bwe_wb[15] == 1'b0)
memsl0hi[vrf_load_addrsl0_wb] = memsl0hi[vrf_load_addrsl0_wb] ;
else if (su_bwe_wb[15] == 1'b1)
memsl0hi[vrf_load_addrsl0_wb] = su_data_to_from[127:120] ;
else
memsl0hi[vrf_load_addrsl0_wb] = 8'hxx ;
if (su_bwe_wb[14] == 1'b0)
memsl0lo[vrf_load_addrsl0_wb] = memsl0lo[vrf_load_addrsl0_wb] ;
else if (su_bwe_wb[14] == 1'b1)
memsl0lo[vrf_load_addrsl0_wb] = su_data_to_from[119:112] ;
else
memsl0lo[vrf_load_addrsl0_wb] = 8'hxx ;
if (su_bwe_wb[13] == 1'b0)
memsl1hi[vrf_load_addrsl1_wb] = memsl1hi[vrf_load_addrsl1_wb] ;
else if (su_bwe_wb[13] == 1'b1)
memsl1hi[vrf_load_addrsl1_wb] = su_data_to_from[111:104] ;
else
memsl1hi[vrf_load_addrsl1_wb] = 8'hxx ;
if (su_bwe_wb[12] == 1'b0)
memsl1lo[vrf_load_addrsl1_wb] = memsl1lo[vrf_load_addrsl1_wb] ;
else if (su_bwe_wb[12] == 1'b1)
memsl1lo[vrf_load_addrsl1_wb] = su_data_to_from[103:96] ;
else
memsl1lo[vrf_load_addrsl1_wb] = 8'hxx ;
if (su_bwe_wb[11] == 1'b0)
memsl2hi[vrf_load_addrsl2_wb] = memsl2hi[vrf_load_addrsl2_wb] ;
else if (su_bwe_wb[11] == 1'b1)
memsl2hi[vrf_load_addrsl2_wb] = su_data_to_from[95:88] ;
else
memsl2hi[vrf_load_addrsl2_wb] = 8'hxx ;
if (su_bwe_wb[10] == 1'b0)
memsl2lo[vrf_load_addrsl2_wb] = memsl2lo[vrf_load_addrsl2_wb] ;
else if (su_bwe_wb[10] == 1'b1)
memsl2lo[vrf_load_addrsl2_wb] = su_data_to_from[87:80] ;
else
memsl2lo[vrf_load_addrsl2_wb] = 8'hxx ;
if (su_bwe_wb[9] == 1'b0)
memsl3hi[vrf_load_addrsl3_wb] = memsl3hi[vrf_load_addrsl3_wb] ;
else if (su_bwe_wb[9] == 1'b1)
memsl3hi[vrf_load_addrsl3_wb] = su_data_to_from[79:72] ;
else
memsl3hi[vrf_load_addrsl3_wb] = 8'hxx ;
if (su_bwe_wb[8] == 1'b0)
memsl3lo[vrf_load_addrsl3_wb] = memsl3lo[vrf_load_addrsl3_wb] ;
else if (su_bwe_wb[8] == 1'b1)
memsl3lo[vrf_load_addrsl3_wb] = su_data_to_from[71:64] ;
else
memsl3lo[vrf_load_addrsl3_wb] = 8'hxx ;
if (su_bwe_wb[7] == 1'b0)
memsl4hi[vrf_load_addrsl4_wb] = memsl4hi[vrf_load_addrsl4_wb] ;
else if (su_bwe_wb[7] == 1'b1)
memsl4hi[vrf_load_addrsl4_wb] = su_data_to_from[63:56] ;
else
memsl4hi[vrf_load_addrsl4_wb] = 8'hxx ;
if (su_bwe_wb[6] == 1'b0)
memsl4lo[vrf_load_addrsl4_wb] = memsl4lo[vrf_load_addrsl4_wb] ;
else if (su_bwe_wb[6] == 1'b1)
memsl4lo[vrf_load_addrsl4_wb] = su_data_to_from[55:48] ;
else
memsl4lo[vrf_load_addrsl4_wb] = 8'hxx ;
if (su_bwe_wb[5] == 1'b0)
memsl5hi[vrf_load_addrsl5_wb] = memsl5hi[vrf_load_addrsl5_wb] ;
else if (su_bwe_wb[5] == 1'b1)
memsl5hi[vrf_load_addrsl5_wb] = su_data_to_from[47:40] ;
else
memsl5hi[vrf_load_addrsl5_wb] = 8'hxx ;
if (su_bwe_wb[4] == 1'b0)
memsl5lo[vrf_load_addrsl5_wb] = memsl5lo[vrf_load_addrsl5_wb] ;
else if (su_bwe_wb[4] == 1'b1)
memsl5lo[vrf_load_addrsl5_wb] = su_data_to_from[39:32] ;
else
memsl5lo[vrf_load_addrsl5_wb] = 8'hxx ;
if (su_bwe_wb[3] == 1'b0)
memsl6hi[vrf_load_addrsl6_wb] = memsl6hi[vrf_load_addrsl6_wb] ;
else if (su_bwe_wb[3] == 1'b1)
memsl6hi[vrf_load_addrsl6_wb] = su_data_to_from[31:24] ;
else
memsl6hi[vrf_load_addrsl6_wb] = 8'hxx ;
if (su_bwe_wb[2] == 1'b0)
memsl6lo[vrf_load_addrsl6_wb] = memsl6lo[vrf_load_addrsl6_wb] ;
else if (su_bwe_wb[2] == 1'b1)
memsl6lo[vrf_load_addrsl6_wb] = su_data_to_from[23:16] ;
else
memsl7lo[vrf_load_addrsl6_wb] = 8'hxx ;
if (su_bwe_wb[1] == 1'b0)
memsl7hi[vrf_load_addrsl7_wb] = memsl7hi[vrf_load_addrsl7_wb] ;
else if (su_bwe_wb[1] == 1'b1)
memsl7hi[vrf_load_addrsl7_wb] = su_data_to_from[15:8] ;
else
memsl7hi[vrf_load_addrsl7_wb] = 8'hxx ;
if (su_bwe_wb[0] == 1'b0)
memsl7lo[vrf_load_addrsl7_wb] = memsl7lo[vrf_load_addrsl7_wb] ;
else if (su_bwe_wb[0] == 1'b1)
memsl7lo[vrf_load_addrsl7_wb] = su_data_to_from[7:0] ;
else
memsl7lo[vrf_load_addrsl7_wb] = 8'hxx ;
end
/*
* vd write port functionality
*/
// always @(vct_wbv_wr_en_wb or su_vd_addr_wb or vdp_rslt_data_wb)
always @(negedge clk)
begin
if (vct_wbv_wr_en_wb[7] == 1'b0)
begin
memsl0hi[su_vd_addr_wb] = memsl0hi[su_vd_addr_wb] ;
memsl0lo[su_vd_addr_wb] = memsl0lo[su_vd_addr_wb] ;
end
else if (vct_wbv_wr_en_wb[7] == 1'b1)
begin
memsl0hi[su_vd_addr_wb] = vdp_rslt_data_wb[127:120] ;
memsl0lo[su_vd_addr_wb] = vdp_rslt_data_wb[119:112] ;
end
else
begin
memsl0hi[su_vd_addr_wb] = 8'hxx ;
memsl0lo[su_vd_addr_wb] = 8'hxx ;
end
if (vct_wbv_wr_en_wb[6] == 1'b0)
begin
memsl1hi[su_vd_addr_wb] = memsl1hi[su_vd_addr_wb] ;
memsl1lo[su_vd_addr_wb] = memsl1lo[su_vd_addr_wb] ;
end
else if (vct_wbv_wr_en_wb[6] == 1'b1)
begin
memsl1hi[su_vd_addr_wb] = vdp_rslt_data_wb[111:104] ;
memsl1lo[su_vd_addr_wb] = vdp_rslt_data_wb[103:96] ;
end
else
begin
memsl1hi[su_vd_addr_wb] = 8'hxx ;
memsl1lo[su_vd_addr_wb] = 8'hxx ;
end
if (vct_wbv_wr_en_wb[5] == 1'b0)
begin
memsl2hi[su_vd_addr_wb] = memsl2hi[su_vd_addr_wb] ;
memsl2lo[su_vd_addr_wb] = memsl2lo[su_vd_addr_wb] ;
end
else if (vct_wbv_wr_en_wb[5] == 1'b1)
begin
memsl2hi[su_vd_addr_wb] = vdp_rslt_data_wb[95:88] ;
memsl2lo[su_vd_addr_wb] = vdp_rslt_data_wb[87:80] ;
end
else
begin
memsl2hi[su_vd_addr_wb] = 8'hxx ;
memsl2lo[su_vd_addr_wb] = 8'hxx ;
end
if (vct_wbv_wr_en_wb[4] == 1'b0)
begin
memsl3hi[su_vd_addr_wb] = memsl3hi[su_vd_addr_wb] ;
memsl3lo[su_vd_addr_wb] = memsl3lo[su_vd_addr_wb] ;
end
else if (vct_wbv_wr_en_wb[4] == 1'b1)
begin
memsl3hi[su_vd_addr_wb] = vdp_rslt_data_wb[79:72] ;
memsl3lo[su_vd_addr_wb] = vdp_rslt_data_wb[71:64] ;
end
else
begin
memsl3hi[su_vd_addr_wb] = 8'hxx ;
memsl3lo[su_vd_addr_wb] = 8'hxx ;
end
if (vct_wbv_wr_en_wb[3] == 1'b0)
begin
memsl4hi[su_vd_addr_wb] = memsl4hi[su_vd_addr_wb] ;
memsl4lo[su_vd_addr_wb] = memsl4lo[su_vd_addr_wb] ;
end
else if (vct_wbv_wr_en_wb[3] == 1'b1)
begin
memsl4hi[su_vd_addr_wb] = vdp_rslt_data_wb[63:56] ;
memsl4lo[su_vd_addr_wb] = vdp_rslt_data_wb[55:48] ;
end
else
begin
memsl4hi[su_vd_addr_wb] = 8'hxx ;
memsl4lo[su_vd_addr_wb] = 8'hxx ;
end
if (vct_wbv_wr_en_wb[2] == 1'b0)
begin
memsl5hi[su_vd_addr_wb] = memsl5hi[su_vd_addr_wb] ;
memsl5lo[su_vd_addr_wb] = memsl5lo[su_vd_addr_wb] ;
end
else if (vct_wbv_wr_en_wb[2] == 1'b1)
begin
memsl5hi[su_vd_addr_wb] = vdp_rslt_data_wb[47:40] ;
memsl5lo[su_vd_addr_wb] = vdp_rslt_data_wb[39:32] ;
end
else
begin
memsl5hi[su_vd_addr_wb] = 8'hxx ;
memsl5lo[su_vd_addr_wb] = 8'hxx ;
end
if (vct_wbv_wr_en_wb[1] == 1'b0)
begin
memsl6hi[su_vd_addr_wb] = memsl6hi[su_vd_addr_wb] ;
memsl6lo[su_vd_addr_wb] = memsl6lo[su_vd_addr_wb] ;
end
else if (vct_wbv_wr_en_wb[1] == 1'b1)
begin
memsl6hi[su_vd_addr_wb] = vdp_rslt_data_wb[31:24] ;
memsl6lo[su_vd_addr_wb] = vdp_rslt_data_wb[23:16] ;
end
else
begin
memsl6hi[su_vd_addr_wb] = 8'hxx ;
memsl6lo[su_vd_addr_wb] = 8'hxx ;
end
if (vct_wbv_wr_en_wb[0] == 1'b0)
begin
memsl7hi[su_vd_addr_wb] = memsl7hi[su_vd_addr_wb] ;
memsl7lo[su_vd_addr_wb] = memsl7lo[su_vd_addr_wb] ;
end
else if (vct_wbv_wr_en_wb[0] == 1'b1)
begin
memsl7hi[su_vd_addr_wb] = vdp_rslt_data_wb[15:8] ;
memsl7lo[su_vd_addr_wb] = vdp_rslt_data_wb[7:0] ;
end
else
begin
memsl7hi[su_vd_addr_wb] = 8'hxx ;
memsl7lo[su_vd_addr_wb] = 8'hxx ;
end
end
/*
* Collision detection if two write ports try to write the same address.
* Write x data and set error flag if writes collide.
*/
always @(negedge clk)
begin
write_conflict = 0;
if ( (vct_wbv_wr_en_wb[7] == 1'b1) &&
( (su_bwe_wb[15] == 1'b1) || (su_bwe_wb[14] == 1'b1) ) &&
( su_vd_addr_wb == vrf_load_addrsl0_wb )
)
begin
memsl0hi[su_vd_addr_wb] = 8'hxx ;
memsl0lo[su_vd_addr_wb] = 8'hxx ;
write_conflict = 1;
$display($time," ERROR:Write Conflict slice 0 for 3R/2W regfile");
end
if ( (vct_wbv_wr_en_wb[6] == 1'b1) &&
( (su_bwe_wb[13] == 1'b1) || (su_bwe_wb[12] == 1'b1) ) &&
( su_vd_addr_wb == vrf_load_addrsl1_wb )
)
begin
memsl1hi[su_vd_addr_wb] = 8'hxx ;
memsl1lo[su_vd_addr_wb] = 8'hxx ;
write_conflict = 1;
$display($time," ERROR:Write Conflict slice 1 for 3R/2W regfile");
end
if ( (vct_wbv_wr_en_wb[5] == 1'b1) &&
( (su_bwe_wb[11] == 1'b1) || (su_bwe_wb[10] == 1'b1) ) &&
( su_vd_addr_wb == vrf_load_addrsl2_wb )
)
begin
memsl2hi[su_vd_addr_wb] = 8'hxx ;
memsl2lo[su_vd_addr_wb] = 8'hxx ;
write_conflict = 1;
$display($time," ERROR:Write Conflict slice 2 for 3R/2W regfile");
end
if ( (vct_wbv_wr_en_wb[4] == 1'b1) &&
( (su_bwe_wb[9] == 1'b1) || (su_bwe_wb[8] == 1'b1) ) &&
( su_vd_addr_wb == vrf_load_addrsl3_wb )
)
begin
memsl3hi[su_vd_addr_wb] = 8'hxx ;
memsl3lo[su_vd_addr_wb] = 8'hxx ;
write_conflict = 1;
$display($time," ERROR:Write Conflict slice 3 for 3R/2W regfile");
end
if ( (vct_wbv_wr_en_wb[3] == 1'b1) &&
( (su_bwe_wb[7] == 1'b1) || (su_bwe_wb[6] == 1'b1) ) &&
( su_vd_addr_wb == vrf_load_addrsl4_wb )
)
begin
memsl4hi[su_vd_addr_wb] = 8'hxx ;
memsl4lo[su_vd_addr_wb] = 8'hxx ;
write_conflict = 1;
$display($time," ERROR:Write Conflict slice 4 for 3R/2W regfile");
end
if ( (vct_wbv_wr_en_wb[2] == 1'b1) &&
( (su_bwe_wb[5] == 1'b1) || (su_bwe_wb[4] == 1'b1) ) &&
( su_vd_addr_wb == vrf_load_addrsl5_wb )
)
begin
memsl5hi[su_vd_addr_wb] = 8'hxx ;
memsl5lo[su_vd_addr_wb] = 8'hxx ;
write_conflict = 1;
$display($time," ERROR:Write Conflict slice 5 for 3R/2W regfile");
end
if ( (vct_wbv_wr_en_wb[1] == 1'b1) &&
( (su_bwe_wb[3] == 1'b1) || (su_bwe_wb[2] == 1'b1) ) &&
( su_vd_addr_wb == vrf_load_addrsl6_wb )
)
begin
memsl6hi[su_vd_addr_wb] = 8'hxx ;
memsl6lo[su_vd_addr_wb] = 8'hxx ;
write_conflict = 1;
$display($time," ERROR:Write Conflict slice 6 for 3R/2W regfile");
end
if ( (vct_wbv_wr_en_wb[0] == 1'b1) &&
( (su_bwe_wb[1] == 1'b1) || (su_bwe_wb[0] == 1'b1) ) &&
( su_vd_addr_wb == vrf_load_addrsl7_wb )
)
begin
memsl7hi[su_vd_addr_wb] = 8'hxx ;
memsl7lo[su_vd_addr_wb] = 8'hxx ;
write_conflict = 1;
$display($time," ERROR:Write Conflict slice 7 for 3R/2W regfile");
end
end
/*
* vt read port data access including scalar mux functionality
*/
always @(clk or su_vt_addr_rd or su_sclrdatasl_rd or
su_qrtdatasl_rd or su_hlfdatasl_rd or su_whldatasl_rd
)
begin
case ( su_qrtdatasl_rd )
2'h1: begin
vrf_qrtdata01_rd = {memsl0hi[su_vt_addr_rd],memsl0lo[su_vt_addr_rd]} ;
vrf_qrtdata23_rd = {memsl2hi[su_vt_addr_rd],memsl2lo[su_vt_addr_rd]} ;
vrf_qrtdata45_rd = {memsl4hi[su_vt_addr_rd],memsl4lo[su_vt_addr_rd]} ;
vrf_qrtdata67_rd = {memsl6hi[su_vt_addr_rd],memsl6lo[su_vt_addr_rd]} ;
end
2'h2: begin
vrf_qrtdata01_rd = {memsl1hi[su_vt_addr_rd],memsl1lo[su_vt_addr_rd]} ;
vrf_qrtdata23_rd = {memsl3hi[su_vt_addr_rd],memsl3lo[su_vt_addr_rd]} ;
vrf_qrtdata45_rd = {memsl5hi[su_vt_addr_rd],memsl5lo[su_vt_addr_rd]} ;
vrf_qrtdata67_rd = {memsl7hi[su_vt_addr_rd],memsl7lo[su_vt_addr_rd]} ;
end
default :
begin
vrf_qrtdata01_rd = 16'hxxxx ;
vrf_qrtdata23_rd = 16'hxxxx ;
vrf_qrtdata45_rd = 16'hxxxx ;
vrf_qrtdata67_rd = 16'hxxxx ;
end
endcase // su_qrtdatasl_rd
case ( su_hlfdatasl_rd )
4'h1: begin
vrf_hlfdata03_rd = {memsl0hi[su_vt_addr_rd],memsl0lo[su_vt_addr_rd]} ;
vrf_hlfdata47_rd = {memsl4hi[su_vt_addr_rd],memsl4lo[su_vt_addr_rd]} ;
end
4'h2: begin
vrf_hlfdata03_rd = {memsl1hi[su_vt_addr_rd],memsl1lo[su_vt_addr_rd]} ;
vrf_hlfdata47_rd = {memsl5hi[su_vt_addr_rd],memsl5lo[su_vt_addr_rd]} ;
end
4'h4: begin
vrf_hlfdata03_rd = {memsl2hi[su_vt_addr_rd],memsl2lo[su_vt_addr_rd]} ;
vrf_hlfdata47_rd = {memsl6hi[su_vt_addr_rd],memsl6lo[su_vt_addr_rd]} ;
end
4'h8: begin
vrf_hlfdata03_rd = {memsl3hi[su_vt_addr_rd],memsl3lo[su_vt_addr_rd]} ;
vrf_hlfdata47_rd = {memsl7hi[su_vt_addr_rd],memsl7lo[su_vt_addr_rd]} ;
end
default :
begin
vrf_hlfdata03_rd = 16'hxxxx ;
vrf_hlfdata47_rd = 16'hxxxx ;
end
endcase // su_hlfdatasl_rd
case ( su_whldatasl_rd )
8'h01: begin
vrf_whldata_rd = {memsl0hi[su_vt_addr_rd],memsl0lo[su_vt_addr_rd]} ;
end
8'h02: begin
vrf_whldata_rd = {memsl1hi[su_vt_addr_rd],memsl1lo[su_vt_addr_rd]} ;
end
8'h04: begin
vrf_whldata_rd = {memsl2hi[su_vt_addr_rd],memsl2lo[su_vt_addr_rd]} ;
end
8'h08: begin
vrf_whldata_rd = {memsl3hi[su_vt_addr_rd],memsl3lo[su_vt_addr_rd]} ;
end
8'h10: begin
vrf_whldata_rd = {memsl4hi[su_vt_addr_rd],memsl4lo[su_vt_addr_rd]} ;
end
8'h20: begin
vrf_whldata_rd = {memsl5hi[su_vt_addr_rd],memsl5lo[su_vt_addr_rd]} ;
end
8'h40: begin
vrf_whldata_rd = {memsl6hi[su_vt_addr_rd],memsl6lo[su_vt_addr_rd]} ;
end
8'h80: begin
vrf_whldata_rd = {memsl7hi[su_vt_addr_rd],memsl7lo[su_vt_addr_rd]} ;
end
default :
begin
vrf_whldata_rd = 16'hxxxx ;
end
endcase // su_whldatasl_rd
case ( su_sclrdatasl_rd )
4'h1: vrf_vt_data_rd = {
memsl0hi[su_vt_addr_rd], memsl0lo[su_vt_addr_rd],
memsl1hi[su_vt_addr_rd], memsl1lo[su_vt_addr_rd],
memsl2hi[su_vt_addr_rd], memsl2lo[su_vt_addr_rd],
memsl3hi[su_vt_addr_rd], memsl3lo[su_vt_addr_rd],
memsl4hi[su_vt_addr_rd], memsl4lo[su_vt_addr_rd],
memsl5hi[su_vt_addr_rd], memsl5lo[su_vt_addr_rd],
memsl6hi[su_vt_addr_rd], memsl6lo[su_vt_addr_rd],
memsl7hi[su_vt_addr_rd], memsl7lo[su_vt_addr_rd]
} ;
4'h2: vrf_vt_data_rd = {
vrf_qrtdata01_rd, vrf_qrtdata01_rd,
vrf_qrtdata23_rd, vrf_qrtdata23_rd,
vrf_qrtdata45_rd, vrf_qrtdata45_rd,
vrf_qrtdata67_rd, vrf_qrtdata67_rd
} ;
4'h4: vrf_vt_data_rd = {
vrf_hlfdata03_rd, vrf_hlfdata03_rd,
vrf_hlfdata03_rd, vrf_hlfdata03_rd,
vrf_hlfdata47_rd, vrf_hlfdata47_rd,
vrf_hlfdata47_rd, vrf_hlfdata47_rd
} ;
4'h8: vrf_vt_data_rd = {
vrf_whldata_rd, vrf_whldata_rd,
vrf_whldata_rd, vrf_whldata_rd,
vrf_whldata_rd, vrf_whldata_rd,
vrf_whldata_rd, vrf_whldata_rd
} ;
default : vrf_vt_data_rd = 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ;
endcase // su_sclrdatasl_rd
end
assign vrf_div_input_rd = vrf_whldata_rd[15:0];
always @(posedge clk)
begin
vrf_vt_datarg_mu <= !reset_l ? 128'h0
: su_instvld_rd ? vrf_vt_data_rd
: vrf_vt_datarg_mu ;
end
assign vrf_vt_data_mu = vrf_vt_datarg_mu ;
/*
* vs read port read data access
*/
assign vrf_vs_rfout_rd = { memsl0hi[su_vs_addr_rd], memsl0lo[su_vs_addr_rd],
memsl1hi[su_vs_addr_rd], memsl1lo[su_vs_addr_rd],
memsl2hi[su_vs_addr_rd], memsl2lo[su_vs_addr_rd],
memsl3hi[su_vs_addr_rd], memsl3lo[su_vs_addr_rd],
memsl4hi[su_vs_addr_rd], memsl4lo[su_vs_addr_rd],
memsl5hi[su_vs_addr_rd], memsl5lo[su_vs_addr_rd],
memsl6hi[su_vs_addr_rd], memsl6lo[su_vs_addr_rd],
memsl7hi[su_vs_addr_rd], memsl7lo[su_vs_addr_rd]
} ;
always @(posedge clk)
begin
vrf_vs_datarg_mu <= !reset_l ? 128'h0
: su_instvld_rd ? vrf_vs_rfout_rd
: vrf_vs_datarg_mu ;
end
assign vrf_vs_data_mu = vrf_vs_datarg_mu ;
/*
* Store read port read data access
*/
wire [4:0] vrf_store_addrsl0_rd; /* register number for store read data slice 0 */
wire [4:0] vrf_store_addrsl1_rd; /* register number for store read data slice 1 */
wire [4:0] vrf_store_addrsl2_rd; /* register number for store read data slice 2 */
wire [4:0] vrf_store_addrsl3_rd; /* register number for store read data slice 3 */
wire [4:0] vrf_store_addrsl4_rd; /* register number for store read data slice 4 */
wire [4:0] vrf_store_addrsl5_rd; /* register number for store read data slice 5 */
wire [4:0] vrf_store_addrsl6_rd; /* register number for store read data slice 6 */
wire [4:0] vrf_store_addrsl7_rd; /* register number for store read data slice 7 */
assign vrf_store_addrsl0_rd = !su_xposeop_rd ? su_st_rnum_rd
: su_xp_rnum_rd ;
assign vrf_store_addrsl1_rd = !su_xposeop_rd ? su_st_rnum_rd
: { su_xp_rnum_rd[4:3],
(su_xp_rnum_rd[2:0] + 3'h1)&3'h7
} ;
assign vrf_store_addrsl2_rd = !su_xposeop_rd ? su_st_rnum_rd
: { su_xp_rnum_rd[4:3],
(su_xp_rnum_rd[2:0] + 3'h2)&3'h7
} ;
assign vrf_store_addrsl3_rd = !su_xposeop_rd ? su_st_rnum_rd
: { su_xp_rnum_rd[4:3],
(su_xp_rnum_rd[2:0] + 3'h3)&3'h7
} ;
assign vrf_store_addrsl4_rd = !su_xposeop_rd ? su_st_rnum_rd
: { su_xp_rnum_rd[4:3],
(su_xp_rnum_rd[2:0] + 3'h4)&3'h7
} ;
assign vrf_store_addrsl5_rd = !su_xposeop_rd ? su_st_rnum_rd
: { su_xp_rnum_rd[4:3],
(su_xp_rnum_rd[2:0] + 3'h5)&3'h7
} ;
assign vrf_store_addrsl6_rd = !su_xposeop_rd ? su_st_rnum_rd
: { su_xp_rnum_rd[4:3],
(su_xp_rnum_rd[2:0] + 3'h6)&3'h7
} ;
assign vrf_store_addrsl7_rd = !su_xposeop_rd ? su_st_rnum_rd
: { su_xp_rnum_rd[4:3],
(su_xp_rnum_rd[2:0] + 3'h7)&3'h7
} ;
always @(posedge clk)
begin
vrf_data_from_mu <= { memsl0hi[vrf_store_addrsl0_rd], memsl0lo[vrf_store_addrsl0_rd],
memsl1hi[vrf_store_addrsl1_rd], memsl1lo[vrf_store_addrsl1_rd],
memsl2hi[vrf_store_addrsl2_rd], memsl2lo[vrf_store_addrsl2_rd],
memsl3hi[vrf_store_addrsl3_rd], memsl3lo[vrf_store_addrsl3_rd],
memsl4hi[vrf_store_addrsl4_rd], memsl4lo[vrf_store_addrsl4_rd],
memsl5hi[vrf_store_addrsl5_rd], memsl5lo[vrf_store_addrsl5_rd],
memsl6hi[vrf_store_addrsl6_rd], memsl6lo[vrf_store_addrsl6_rd],
memsl7hi[vrf_store_addrsl7_rd], memsl7lo[vrf_store_addrsl7_rd]
} ;
end
/*
* Tristate control for su_data_to_from bus.
*/
wire vrf_datatristen_mu; /* tristate enable for load/store data bus */
asdff #(1, 0) vrfdatatristenffmu (vrf_datatristen_mu, vdp_datatristen_rd, clk, reset_l );
assign su_data_to_from[127:0] = vrf_datatristen_mu ? vrf_data_from_mu[127:0]
: 128'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz ;
endmodule // vurf