ddr.scr
13.8 KB
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/* ddr.scr v1 Frank Berndt
* ddr constraints;
*/
/*
* ddr diff clock to pins;
* memclk -> buf -> ( buf -> io -> pin, inv -> io -> pin );
* tap off memclk tree only once to eliminate memclk tree skew;
* dont_touch all involved cells and wires;
* PAD_* and pad_* are already dont_touch above;
*/
set_dont_touch mclk_tap
set_dont_touch mclk_buf
set_dont_touch { mclk_plus mclk_minus }
set_min_delay 1.1 -from MEMCLK -to { PAD_MCLK0 PAD_MCLK1 }
set_max_delay 1.2 -from MEMCLK -to { PAD_MCLK0 PAD_MCLK1 }
/*
* create virtual clock at DDR chip;
* delayed by t[out] + board delay of 1/4 memclk;
* set to uncertainty of memclk;
*/
create_clock -name DDRCLK -period 4.5 -waveform { 2.25 4.5 }
set_clock_skew -uncertainty 0.450 DDRCLK /* delayed MEMCLK */
/*
* ddr address/ctrl path;
* single-data rate, outputs synchronous to MEMCLK;
* remember that DDR sees delayed clock;
*/
set_output_delay 2.6 -clock DDRCLK -max find(port, "PAD_MBANK*")
set_output_delay 2.6 -clock DDRCLK -max find(port, "PAD_MADDR*")
set_output_delay 2.6 -clock DDRCLK -max { PAD_MRAS PAD_MCAS PAD_MWE PAD_MCKE }
/*
* ddr output data path;
* double-date rate, synchronous to MEMCLK;
* remember that DDR sees delayed clock;
* strobes have board delays to center data;
*/
set_dont_touch find(net, "mdata_out*")
set_dont_touch find(cell, "ddr_domux*")
set_dont_touch find(net, "mdqm_out*")
set_dont_touch find(cell, "ddr_momux*")
set_dont_touch find(net, "ddr_strobe_out*")
set_dont_touch find(cell, "ddr_somux*")
set_dont_touch find(cell, "ddr_d4inv*")
set_dont_touch find(net, "ddr_strobe_on*")
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA0
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA1
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA2
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA3
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA4
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA5
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA6
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA7
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA8
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA9
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA10
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA11
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA12
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA13
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA14
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA15
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA16
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA17
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA18
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA19
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA20
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA21
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA22
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA23
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA24
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA25
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA26
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA27
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA28
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA29
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA30
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA31
set_min_delay 1.2 -from MEMCLK -to PAD_MDQM0
set_min_delay 1.2 -from MEMCLK -to PAD_MDQM1
set_min_delay 1.2 -from MEMCLK -to PAD_MDQM2
set_min_delay 1.2 -from MEMCLK -to PAD_MDQM3
set_min_delay 1.2 -from MEMCLK -to PAD_MDQS0
set_min_delay 1.2 -from MEMCLK -to PAD_MDQS1
set_min_delay 1.2 -from MEMCLK -to PAD_MDQS2
set_min_delay 1.2 -from MEMCLK -to PAD_MDQS3
set_min_delay 1.4 -from { ddr_do_p_reg_0_ ddr_do_n_reg_0_ } -to PAD_MDATA0
set_min_delay 1.4 -from { ddr_do_p_reg_1_ ddr_do_n_reg_1_ } -to PAD_MDATA1
set_min_delay 1.4 -from { ddr_do_p_reg_2_ ddr_do_n_reg_2_ } -to PAD_MDATA2
set_min_delay 1.4 -from { ddr_do_p_reg_3_ ddr_do_n_reg_3_ } -to PAD_MDATA3
set_min_delay 1.4 -from { ddr_do_p_reg_4_ ddr_do_n_reg_4_ } -to PAD_MDATA4
set_min_delay 1.4 -from { ddr_do_p_reg_5_ ddr_do_n_reg_5_ } -to PAD_MDATA5
set_min_delay 1.4 -from { ddr_do_p_reg_6_ ddr_do_n_reg_6_ } -to PAD_MDATA6
set_min_delay 1.4 -from { ddr_do_p_reg_7_ ddr_do_n_reg_7_ } -to PAD_MDATA7
set_min_delay 1.4 -from { ddr_do_p_reg_8_ ddr_do_n_reg_8_ } -to PAD_MDATA8
set_min_delay 1.4 -from { ddr_do_p_reg_9_ ddr_do_n_reg_9_ } -to PAD_MDATA9
set_min_delay 1.4 -from { ddr_do_p_reg_10_ ddr_do_n_reg_10_ } -to PAD_MDATA10
set_min_delay 1.4 -from { ddr_do_p_reg_11_ ddr_do_n_reg_11_ } -to PAD_MDATA11
set_min_delay 1.4 -from { ddr_do_p_reg_12_ ddr_do_n_reg_12_ } -to PAD_MDATA12
set_min_delay 1.4 -from { ddr_do_p_reg_13_ ddr_do_n_reg_13_ } -to PAD_MDATA13
set_min_delay 1.4 -from { ddr_do_p_reg_14_ ddr_do_n_reg_14_ } -to PAD_MDATA14
set_min_delay 1.4 -from { ddr_do_p_reg_15_ ddr_do_n_reg_15_ } -to PAD_MDATA15
set_min_delay 1.4 -from { ddr_do_p_reg_16_ ddr_do_n_reg_16_ } -to PAD_MDATA16
set_min_delay 1.4 -from { ddr_do_p_reg_17_ ddr_do_n_reg_17_ } -to PAD_MDATA17
set_min_delay 1.4 -from { ddr_do_p_reg_18_ ddr_do_n_reg_18_ } -to PAD_MDATA18
set_min_delay 1.4 -from { ddr_do_p_reg_19_ ddr_do_n_reg_19_ } -to PAD_MDATA19
set_min_delay 1.4 -from { ddr_do_p_reg_20_ ddr_do_n_reg_20_ } -to PAD_MDATA20
set_min_delay 1.4 -from { ddr_do_p_reg_21_ ddr_do_n_reg_21_ } -to PAD_MDATA21
set_min_delay 1.4 -from { ddr_do_p_reg_22_ ddr_do_n_reg_22_ } -to PAD_MDATA22
set_min_delay 1.4 -from { ddr_do_p_reg_23_ ddr_do_n_reg_23_ } -to PAD_MDATA23
set_min_delay 1.4 -from { ddr_do_p_reg_24_ ddr_do_n_reg_24_ } -to PAD_MDATA24
set_min_delay 1.4 -from { ddr_do_p_reg_25_ ddr_do_n_reg_25_ } -to PAD_MDATA25
set_min_delay 1.4 -from { ddr_do_p_reg_26_ ddr_do_n_reg_26_ } -to PAD_MDATA26
set_min_delay 1.4 -from { ddr_do_p_reg_27_ ddr_do_n_reg_27_ } -to PAD_MDATA27
set_min_delay 1.4 -from { ddr_do_p_reg_28_ ddr_do_n_reg_28_ } -to PAD_MDATA28
set_min_delay 1.4 -from { ddr_do_p_reg_29_ ddr_do_n_reg_29_ } -to PAD_MDATA29
set_min_delay 1.4 -from { ddr_do_p_reg_30_ ddr_do_n_reg_30_ } -to PAD_MDATA30
set_min_delay 1.4 -from { ddr_do_p_reg_31_ ddr_do_n_reg_31_ } -to PAD_MDATA31
set_min_delay 1.4 -from { ddr_dqm_p_reg_0_ ddr_dqm_n_reg_0_ } -to PAD_MDQM0
set_min_delay 1.4 -from { ddr_dqm_p_reg_1_ ddr_dqm_n_reg_1_ } -to PAD_MDQM1
set_min_delay 1.4 -from { ddr_dqm_p_reg_2_ ddr_dqm_n_reg_2_ } -to PAD_MDQM2
set_min_delay 1.4 -from { ddr_dqm_p_reg_3_ ddr_dqm_n_reg_3_ } -to PAD_MDQM3
set_min_delay 0.6 -from ddr_wr_n_reg -to find(cell, "ddr_somux*")
set_min_delay 1.4 -from ddr_moe_reg_0_ -to { PAD_MDATA0 PAD_MDATA1 PAD_MDATA2 PAD_MDATA3 PAD_MDQS0 }
set_min_delay 1.4 -from ddr_moe_reg_1_ -to { PAD_MDATA4 PAD_MDATA5 PAD_MDATA6 PAD_MDATA7 }
set_min_delay 1.4 -from ddr_moe_reg_2_ -to { PAD_MDATA8 PAD_MDATA9 PAD_MDATA10 PAD_MDATA11 PAD_MDQS1 }
set_min_delay 1.4 -from ddr_moe_reg_3_ -to { PAD_MDATA12 PAD_MDATA13 PAD_MDATA14 PAD_MDATA15 }
set_min_delay 1.4 -from ddr_moe_reg_4_ -to { PAD_MDATA16 PAD_MDATA17 PAD_MDATA18 PAD_MDATA19 PAD_MDQS2 }
set_min_delay 1.4 -from ddr_moe_reg_5_ -to { PAD_MDATA20 PAD_MDATA21 PAD_MDATA22 PAD_MDATA23 }
set_min_delay 1.4 -from ddr_moe_reg_6_ -to { PAD_MDATA24 PAD_MDATA25 PAD_MDATA26 PAD_MDATA27 PAD_MDQS3 }
set_min_delay 1.4 -from ddr_moe_reg_7_ -to { PAD_MDATA28 PAD_MDATA29 PAD_MDATA30 PAD_MDATA31 }
/*
* max delays;
*/
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA0
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA1
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA2
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA3
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA4
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA5
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA6
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA7
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA8
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA9
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA10
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA11
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA12
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA13
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA14
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA15
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA16
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA17
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA18
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA19
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA20
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA21
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA22
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA23
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA24
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA25
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA26
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA27
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA28
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA29
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA30
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA31
set_max_delay 1.4 -from MEMCLK -to PAD_MDQM0
set_max_delay 1.4 -from MEMCLK -to PAD_MDQM1
set_max_delay 1.4 -from MEMCLK -to PAD_MDQM2
set_max_delay 1.4 -from MEMCLK -to PAD_MDQM3
set_max_delay 1.4 -from MEMCLK -to PAD_MDQS0
set_max_delay 1.4 -from MEMCLK -to PAD_MDQS1
set_max_delay 1.4 -from MEMCLK -to PAD_MDQS2
set_max_delay 1.4 -from MEMCLK -to PAD_MDQS3
set_max_delay 1.6 -from { ddr_do_p_reg_0_ ddr_do_n_reg_0_ } -to PAD_MDATA0
set_max_delay 1.6 -from { ddr_do_p_reg_1_ ddr_do_n_reg_1_ } -to PAD_MDATA1
set_max_delay 1.6 -from { ddr_do_p_reg_2_ ddr_do_n_reg_2_ } -to PAD_MDATA2
set_max_delay 1.6 -from { ddr_do_p_reg_3_ ddr_do_n_reg_3_ } -to PAD_MDATA3
set_max_delay 1.6 -from { ddr_do_p_reg_4_ ddr_do_n_reg_4_ } -to PAD_MDATA4
set_max_delay 1.6 -from { ddr_do_p_reg_5_ ddr_do_n_reg_5_ } -to PAD_MDATA5
set_max_delay 1.6 -from { ddr_do_p_reg_6_ ddr_do_n_reg_6_ } -to PAD_MDATA6
set_max_delay 1.6 -from { ddr_do_p_reg_7_ ddr_do_n_reg_7_ } -to PAD_MDATA7
set_max_delay 1.6 -from { ddr_do_p_reg_8_ ddr_do_n_reg_8_ } -to PAD_MDATA8
set_max_delay 1.6 -from { ddr_do_p_reg_9_ ddr_do_n_reg_9_ } -to PAD_MDATA9
set_max_delay 1.6 -from { ddr_do_p_reg_10_ ddr_do_n_reg_10_ } -to PAD_MDATA10
set_max_delay 1.6 -from { ddr_do_p_reg_11_ ddr_do_n_reg_11_ } -to PAD_MDATA11
set_max_delay 1.6 -from { ddr_do_p_reg_12_ ddr_do_n_reg_12_ } -to PAD_MDATA12
set_max_delay 1.6 -from { ddr_do_p_reg_13_ ddr_do_n_reg_13_ } -to PAD_MDATA13
set_max_delay 1.6 -from { ddr_do_p_reg_14_ ddr_do_n_reg_14_ } -to PAD_MDATA14
set_max_delay 1.6 -from { ddr_do_p_reg_15_ ddr_do_n_reg_15_ } -to PAD_MDATA15
set_max_delay 1.6 -from { ddr_do_p_reg_16_ ddr_do_n_reg_16_ } -to PAD_MDATA16
set_max_delay 1.6 -from { ddr_do_p_reg_17_ ddr_do_n_reg_17_ } -to PAD_MDATA17
set_max_delay 1.6 -from { ddr_do_p_reg_18_ ddr_do_n_reg_18_ } -to PAD_MDATA18
set_max_delay 1.6 -from { ddr_do_p_reg_19_ ddr_do_n_reg_19_ } -to PAD_MDATA19
set_max_delay 1.6 -from { ddr_do_p_reg_20_ ddr_do_n_reg_20_ } -to PAD_MDATA20
set_max_delay 1.6 -from { ddr_do_p_reg_21_ ddr_do_n_reg_21_ } -to PAD_MDATA21
set_max_delay 1.6 -from { ddr_do_p_reg_22_ ddr_do_n_reg_22_ } -to PAD_MDATA22
set_max_delay 1.6 -from { ddr_do_p_reg_23_ ddr_do_n_reg_23_ } -to PAD_MDATA23
set_max_delay 1.6 -from { ddr_do_p_reg_24_ ddr_do_n_reg_24_ } -to PAD_MDATA24
set_max_delay 1.6 -from { ddr_do_p_reg_25_ ddr_do_n_reg_25_ } -to PAD_MDATA25
set_max_delay 1.6 -from { ddr_do_p_reg_26_ ddr_do_n_reg_26_ } -to PAD_MDATA26
set_max_delay 1.6 -from { ddr_do_p_reg_27_ ddr_do_n_reg_27_ } -to PAD_MDATA27
set_max_delay 1.6 -from { ddr_do_p_reg_28_ ddr_do_n_reg_28_ } -to PAD_MDATA28
set_max_delay 1.6 -from { ddr_do_p_reg_29_ ddr_do_n_reg_29_ } -to PAD_MDATA29
set_max_delay 1.6 -from { ddr_do_p_reg_30_ ddr_do_n_reg_30_ } -to PAD_MDATA30
set_max_delay 1.6 -from { ddr_do_p_reg_31_ ddr_do_n_reg_31_ } -to PAD_MDATA31
set_max_delay 1.6 -from { ddr_dqm_p_reg_0_ ddr_dqm_n_reg_0_ } -to PAD_MDQM0
set_max_delay 1.6 -from { ddr_dqm_p_reg_1_ ddr_dqm_n_reg_1_ } -to PAD_MDQM1
set_max_delay 1.6 -from { ddr_dqm_p_reg_2_ ddr_dqm_n_reg_2_ } -to PAD_MDQM2
set_max_delay 1.6 -from { ddr_dqm_p_reg_3_ ddr_dqm_n_reg_3_ } -to PAD_MDQM3
set_max_delay 1.6 -from ddr_wr_n_reg -to find(cell, "ddr_somux*")
set_max_delay 1.8 -from ddr_moe_reg_0_ -to { PAD_MDATA0 PAD_MDATA1 PAD_MDATA2 PAD_MDATA3 PAD_MDQS0 }
set_max_delay 1.8 -from ddr_moe_reg_1_ -to { PAD_MDATA4 PAD_MDATA5 PAD_MDATA6 PAD_MDATA7 }
set_max_delay 1.8 -from ddr_moe_reg_2_ -to { PAD_MDATA8 PAD_MDATA9 PAD_MDATA10 PAD_MDATA11 PAD_MDQS1 }
set_max_delay 1.8 -from ddr_moe_reg_3_ -to { PAD_MDATA12 PAD_MDATA13 PAD_MDATA14 PAD_MDATA15 }
set_max_delay 1.8 -from ddr_moe_reg_4_ -to { PAD_MDATA16 PAD_MDATA17 PAD_MDATA18 PAD_MDATA19 PAD_MDQS2 }
set_max_delay 1.8 -from ddr_moe_reg_5_ -to { PAD_MDATA20 PAD_MDATA21 PAD_MDATA22 PAD_MDATA23 }
set_max_delay 1.8 -from ddr_moe_reg_6_ -to { PAD_MDATA24 PAD_MDATA25 PAD_MDATA26 PAD_MDATA27 PAD_MDQS3 }
set_max_delay 1.8 -from ddr_moe_reg_7_ -to { PAD_MDATA28 PAD_MDATA29 PAD_MDATA30 PAD_MDATA31 }
/*
* ddr input data path;
* double-date rate, synchronous to strobes;
* remember that DDR drives strobe like a data pin;
* delay on board centers strobes with regards to data;
*/
set_dont_touch find(net, "ddr_strobe_*")
set_dont_touch find(cell, "ddr_strbinv*")
set_dont_touch find(cell, "ddr_strbmux*")
set_dont_touch find(cell, "ddr_strbfan*")
set_dont_touch find(cell, "ddr_strbclk*")
/*
* strobe clocks at bb;
* use clock uncertainty to describe tDQSCK (data/strobe jitter);
* clock phase is chosen to minimize ddr_mdin -> mdin paths;
* strobe-reversal on means inverted strobe clocks;
*/
create_clock -name BBSTB -period 4.5 -waveform { 3.5 5.75 } { \
ddr_strbclk0/N01 ddr_strbclk1/N01 ddr_strbclk2/N01 ddr_strbclk3/N01 \
ddr_strbclk4/N01 ddr_strbclk5/N01 ddr_strbclk6/N01 ddr_strbclk7/N01 }
set_dont_touch_network { \
ddr_strbclk0/N01 ddr_strbclk1/N01 ddr_strbclk2/N01 ddr_strbclk3/N01 \
ddr_strbclk4/N01 ddr_strbclk5/N01 ddr_strbclk6/N01 ddr_strbclk7/N01 }
set_clock_skew -uncertainty 0.5 BBSTB
/*
* create two virtual clocks to describe strobes;
* external virtual flop is clocked on both edges;
* must make opposite edges false paths;
*/
create_clock -name BBSTB_P -period 4.5 -waveform { 3.5 5.75 }
create_clock -name BBSTB_N -period 4.5 -waveform { 5.75 8.0 }
set_input_delay 2.8 -clock BBSTB_P -max find(port, "PAD_MDATA*")
set_input_delay 2.8 -clock BBSTB_N -max find(port, "PAD_MDATA*") -add_delay
set_false_path -from BBSTB_N -to find(cell, "ddr_mdin_p*")
set_false_path -from BBSTB_P -to find(cell, "ddr_mdin_n*")