io_ddrctl_OUT.tcl
3.38 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
set_load -wire_load 15 [get_ports {PAD_MRAS}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {mras_out_reg/*}] \
-to [get_ports {PAD_MRAS}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MCAS}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {mcas_out_reg/*}] \
-to [get_ports {PAD_MCAS}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MWE}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {mwe_out_reg/*}] \
-to [get_ports {PAD_MWE}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MBANK1}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {mbank_out_reg_1_/*}] \
-to [get_ports {PAD_MBANK1}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MBANK0}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {mbank_out_reg_0_/*}] \
-to [get_ports {PAD_MBANK0}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR12}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_12_/*}] \
-to [get_ports {PAD_MADDR12}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR11}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_11_/*}] \
-to [get_ports {PAD_MADDR11}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR10}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_10_/*}] \
-to [get_ports {PAD_MADDR10}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR9}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_9_/*}] \
-to [get_ports {PAD_MADDR9}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR8}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_8_/*}] \
-to [get_ports {PAD_MADDR8}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR7}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_7_/*}] \
-to [get_ports {PAD_MADDR7}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR6}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_6_/*}] \
-to [get_ports {PAD_MADDR6}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR5}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_5_/*}] \
-to [get_ports {PAD_MADDR5}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR4}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_4_/*}] \
-to [get_ports {PAD_MADDR4}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR3}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_3_/*}] \
-to [get_ports {PAD_MADDR3}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR2}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_2_/*}] \
-to [get_ports {PAD_MADDR2}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR1}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_1_/*}] \
-to [get_ports {PAD_MADDR1}] \
>> io_ddrctl_OUT.rep
set_load -wire_load 15 [get_ports {PAD_MADDR0}]
report_timing -max_paths 1000 -nworst 10 \
-from [get_pins {maddr_out_reg_0_/*}] \
-to [get_ports {PAD_MADDR0}] \
>> io_ddrctl_OUT.rep