ddr.c
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#include "cpusim.h"
#define CMEM_WORD (*(vu32*)K0BASE)
#define UMEM_WORD (*(vu32*)K1BASE)
#define CMEM64_WORD (*(vu32*)PHYS_TO_K0(DDRRAM64_START))
#define UMEM64_WORD (*(vu32*)PHYS_TO_K1(DDRRAM64_START))
#define CNONMEM_WORD (*(vu32*)PHYS_TO_K0(PI_BUFFER_BASE_REG))
#define UNONMEM_WORD (*(vu32*)PHYS_TO_K1(PI_BUFFER_BASE_REG))
int
main() {
int x;
void (*f0)(void);
static void run(void);
vu32 *p0, *p1;
if (((getcp0reg(C0_CONFIG)&CONFIG_EC) >> 28) != 1)
IO_WRITE(MI_CTRL_REG, MI_CTRL_HARD_RESET|MI_CTRL_DIV_MODE_1_5);
test_preamble();
initICache();
initDCache();
init_ddr();
setcp0reg(C0_SR, SR_CU0|SR_CU1|SR_BEV);
setcp0reg(C0_CONFIG, CONFIG_BE|CONFIG_NONCOHRNT);
p0 = (vu32*)run;
p1 = (vu32*)PHYS_TO_K1(INTERNAL_RAM_START);
f0 = (void(*))K1_TO_K0(p1);
for(x = 0; x < 1024; x++) *p1++ = *p0++;
(*f0)();
message("DDR access test\n");
DBG_JTAG_PASS("DDR access test passed\n");
test_postamble();
return 0;
}
#define DDR_X36_START (K0BASE)
#define DDR_X36_END (K0BASE | 0x00800000)
#define DDR_X64_START (K0BASE | 0x01000000)
#define DDR_X64_END (K0BASE | 0x02000000)
static void run(void)
{
vu32 *p, *e;
int i;
/* Init UI sram for output */
IO_WRITE(0x4a40010, 1);
for (i=0x4a80000; i<0x4a80200; i+=4)
IO_WRITE(i, 0xffffffff);
IO_WRITE(0x4a801D0, getcp0reg(C0_COUNT));
p = (vu32*) DDR_X36_START;
e = (vu32*) DDR_X36_END;
while (p<e) *p++ = (vu32) p;
IO_WRITE(0x4a801D4, getcp0reg(C0_COUNT));
p = (vu32*) DDR_X36_START;
e = (vu32*) DDR_X36_END;
while (p<e) {
if (*p != (vu32) p) {
IO_WRITE(0x4a80000, (vu32) p);
IO_WRITE(0x4a80004, p);
IO_WRITE(0x4a80008, *p);
DBG_JTAG_FAIL("DDR access Failed1\n");
break;
}
p++;
}
IO_WRITE(0x4a801D8, getcp0reg(C0_COUNT));
p = (vu32*) DDR_X36_START;
e = (vu32*) DDR_X36_END;
while (p<e) *p++ = ~((vu32) p);
IO_WRITE(0x4a801Dc, getcp0reg(C0_COUNT));
p = (vu32*) DDR_X36_START;
e = (vu32*) DDR_X36_END;
while (p<e) {
if (*p != (~((vu32) p))) {
IO_WRITE(0x4a80010, (vu32) p);
IO_WRITE(0x4a80014, p);
IO_WRITE(0x4a80018, *p);
DBG_JTAG_FAIL("DDR access Failed2\n");
break;
}
p++;
}
IO_WRITE(0x4a801E0, getcp0reg(C0_COUNT));
p = (vu32*) DDR_X64_START;
e = (vu32*) DDR_X64_END;
while (p<e) *p++ = (vu32) p;
IO_WRITE(0x4a801E4, getcp0reg(C0_COUNT));
p = (vu32*) DDR_X64_START;
e = (vu32*) DDR_X64_END;
while (p<e) {
if (*p != (vu32) p) {
IO_WRITE(0x4a80020, (vu32) p);
IO_WRITE(0x4a80024, p);
IO_WRITE(0x4a80028, *p);
DBG_JTAG_FAIL("DDR access Failed3\n");
break;
}
p++;
}
IO_WRITE(0x4a801E8, getcp0reg(C0_COUNT));
p = (vu32*) DDR_X64_START;
e = (vu32*) DDR_X64_END;
while (p<e) *p++ = ~((vu32)p);
IO_WRITE(0x4a801Ec, getcp0reg(C0_COUNT));
p = (vu32*) DDR_X64_START;
e = (vu32*) DDR_X64_END;
while (p<e) {
if (*p != (~((vu32) p))) {
IO_WRITE(0x4a80030, (vu32) p);
IO_WRITE(0x4a80034, p);
IO_WRITE(0x4a80038, *p);
DBG_JTAG_FAIL("DDR access Failed4\n");
break;
}
*p++;
}
IO_WRITE(0x4a801F0, getcp0reg(C0_COUNT));
message("DDR access test\n");
DBG_JTAG_PASS("DDR access test passed\n");
test_postamble();
return 0;
}