#define BCP_IPC
#include "pi_util.h"

#define __FLASH_VERIFY_INT \
    if(enableIntr) { \
        if(flashCheckClearIntr()!=PASS) \
            return -1; \
    } else if(flashCheckNoIntr()!=PASS) \
        return -1



int flashCtrlPollBusy()
{
    poll_timeout(PI_FLASH_CTRL_REG, PI_FLASH_CTRL_BUSY, 1, Timeouts, FLASHBUSYTIMEOUT);
}



/* write a host buffer of bytes with endian considerations
   so the resulting byte pattern is the same in the piBuffer.

   the bytes arg should be a multiple of 4.
*/
void ioWriteBuffer(u8 *data,u32 bytes,u32 bufStart)
{
    int i;

    /* write the specified pi buffer */
    for(i=0;i<bytes;i+=4)
        IO_WRITE(bufStart+i,H2BE4(*((u32 *)(data+i))));
}


/* read a pi buffer of bytes with endian considerations
   so the resulting byte pattern is the same in the host Buffer.

   the bytes arg should be a multiple of 4.
*/
void ioReadBuffer(u8 *data,u32 bytes,u32 bufStart)
{
    int i;

    /* write the specified pi buffer */
    for(i=0;i<bytes;i+=4)
        *((u32 *)(data+i))=H2BE4(IO_READ(bufStart+i)); 
}


/* setup slowest timing and enable writes */
void initFlash()
{
    /* slow timing, enable write */
    //IO_WRITE(PI_FLASH_CONFIG_REG,0x2207071f); /* period > 15ns */
    //IO_WRITE(PI_FLASH_CONFIG_REG,0x430f0f3f); /* period >= 10ns */
    IO_WRITE(PI_FLASH_CONFIG_REG, 0x753e1f3f);

}

/*
 * eraseBlock()
 *
 *    erase a block of flash. Will check to insure proper 
 *    interrupt action depending on enableIntr arg (i.e., insure
 *    int not generated if not enabled, and int generated if
 *    enabled.
 *
 * Return value
 *
 *    status register value if routine has completed. 
 *    -1 if an error (bad arguments, unexpected behavior
 *    for int) occurs.
 *
 * Arguments
 *
 *  eraseAddr: 
 *    address of block to be erased
 *  devId:     
 *    device ID for block to be erased
 *  statusReadAddr:
 *    address into buffer for reading back the status byte.
 *    The legal range is 0-252 and the address must be 4
 *    byte aligned. 
 *  buffer:
 *    "Data buffer" choice (1 or 0) in PI buffer.
 *  bigDevice:
 *    non-zero means big device (64MB or greater).
 *  enableIntr:
 *    check interrupt is properly generated at each cycle
 */
int eraseBlock(
    u32 eraseAddr,
    u32 devId,
    u32 statusReadAddr,
    u32 buffer,
    int bigDevice,
    int enableIntr)
{
    int ret,i;
    u32 command;

    if(buffer>1 || devId>3 || statusReadAddr>252 || statusReadAddr&3)
        return -1;

    /* paranoid - take care of case where enableIntr "true" is > 1 */
    if(enableIntr)
        enableIntr = 1;
    else
        enableIntr = 0;

    /* setup block address */
    IO_WRITE(PI_FLASH_ADDR_REG,eraseAddr);
#ifdef TOSHIBA_FLASH
    command = 0x8e600400;
#else
    /* multi-cycle command, 0x60 */
    if(bigDevice){
        command = 0x8e600400;
    }
    else{
        command = 0x86600400;
    }
#endif
    command |= PI_CTRL_DEV_SHIFT(devId);
    command |= enableIntr*PI_FLASH_CTRL_INTR;
    IO_WRITE(PI_FLASH_CTRL_REG,command);
    POLL_CTRL_BUSY_TIMEOUT;
    __FLASH_VERIFY_INT;

    _TRACE(DSTATUS, fprintf(LogFp,"address phase of erase complete\n"));

    /* second cycle, 0xd0 */
    IO_WRITE(PI_FLASH_CTRL_REG,0x80d08000 | (enableIntr*PI_FLASH_CTRL_INTR)
        |PI_CTRL_DEV_SHIFT(devId));
    POLL_CTRL_BUSY_TIMEOUT;
    __FLASH_VERIFY_INT;

    _TRACE(DSTATUS, fprintf(LogFp,"block erased, addr %x\n", eraseAddr));

    return statusRead(statusReadAddr,devId,buffer,enableIntr);
}

/*
 * both pointers "data" and "oob" may be null, in which case
 * it is assumed the pi buffer already holds that data.
 *
 * if eccOn=1, the ECC bytes will be computed during the
 * DMA. Since the entire buffer is required to be written (see
 * note below) this will be fine.
 *
 * The status read (0x70 command to flash) will always be to
 * byte zero of the buffer chosen by the piBuffer arg.
 *
 * endian conversion is done so the byte layout in "data"
 * and "oob" match that in the piBuffer.
 *
 * NOTE: for program operations the data in the pi buffer
 *  is always aligned to the beginning of the buffer. So,
 *  even if the program command were to start in the second
 *  half by using commands ( 0x01, 0x80, 0x10 ) the address
 *  issued at the 0x80 must have bit postition 8 low (due to
 *  the OR operation of bit 8 and the command to flash), so
 *  the pi buffer position is in the first half. The same
 *  holds true for the ( 0x50, 0x80, 0x10 ) program sequence.
 *  BUT, since some flash devices (Toshiba) specify the bits
 *  not being programmed must be set to '1' in the buffer
 *  (Samsung appears to automatically initialize the buffer
 *  to zero), we program the entire 528 byte chunk here.
 *  Any partial programming would require a call to this
 *  function where the 528-bytes are managed accordingly
 *  ('1' bits written where no programming is to occur).
 */
int programFullPage(
    u32 addr,     /* start address, must be 512B aligned */
    u32 piBuffer, /* buffer holding data for programming */
    u32 device,   /* device choice */
    uint eccOn,   /* 1 if ecc should be used */
    u8  *data,    /* 512B data to be written. can be null */
    u8  *oob,     /* out-of-band data. if non-null holds 16B */
    u32 piStatBuffer, /* buffer to read status back into */
    int bigDevice,
    int enableIntr
    )
{
    int i;
    int ret;

    if(addr&0x1ff || piBuffer>1 || device>3)
        return -1;
    eccOn&=1;

    /* paranoid - take care of case where enableIntr "true" is > 1 */
    if(enableIntr)
        enableIntr = 1;
    else
        enableIntr = 0;

    if(data){
        /* write the specified pi buffer */
        for(i=0;i<PI_FLASH_PAGE_DATA_SIZE;i+=4)
            IO_WRITE(PI_BUFFER_0_START+piBuffer*PI_FLASH_PAGE_DATA_SIZE+i,
                     H2BE4(*((u32 *)(data+i))));
    }
    if(oob){
        for(i=0;i<PI_FLASH_OOB_SIZE;i+=4)
            IO_WRITE(PI_BUFFER_0_OOB_START+piBuffer*PI_FLASH_OOB_SIZE+i,
                     H2BE4(*((u32 *)(oob+i))));
    }

    _TRACE(DSTATUS, fprintf(LogFp,
           "full page program: data written to pi buffer\n"));

    /* 
     * program page with pi buffer data
     */

    /* setup flash address */
    IO_WRITE(PI_FLASH_ADDR_REG,addr);
    /* multi-cycle command */
    IO_WRITE(PI_FLASH_CTRL_REG, 0x80000000 |
             PI_CTRL_DEV_SHIFT(device)  |
             PI_CTRL_BUF_SHIFT(piBuffer) |
             (enableIntr*PI_FLASH_CTRL_INTR));
    POLL_CTRL_BUSY_TIMEOUT;
    __FLASH_VERIFY_INT;

    /* must insure address bit 8 is zero or the 0x80 command will
       become 0x81 */
    IO_WRITE(PI_FLASH_ADDR_REG,addr&0xfffffeff);
#ifdef TOSHIBA_FLASH
    IO_WRITE(PI_FLASH_CTRL_REG,0xaf800610 |
                 (eccOn*PI_FLASH_CTRL_ECC) |
                 PI_CTRL_DEV_SHIFT(device)  |
                 PI_CTRL_BUF_SHIFT(piBuffer) |
                 (enableIntr*PI_FLASH_CTRL_INTR));
#else
    if(bigDevice){
        IO_WRITE(PI_FLASH_CTRL_REG,0xaf800610 |
                 (eccOn*PI_FLASH_CTRL_ECC) |
                 PI_CTRL_DEV_SHIFT(device)  |
                 PI_CTRL_BUF_SHIFT(piBuffer) |
                 (enableIntr*PI_FLASH_CTRL_INTR));
    }
    else{
        IO_WRITE(PI_FLASH_CTRL_REG,0xa7800610 |
                 (eccOn*PI_FLASH_CTRL_ECC) |
                 PI_CTRL_DEV_SHIFT(device)  |
                 PI_CTRL_BUF_SHIFT(piBuffer) |
                 (enableIntr*PI_FLASH_CTRL_INTR));
    }
#endif
    POLL_CTRL_BUSY_TIMEOUT;
    __FLASH_VERIFY_INT;
    _TRACE(DSTATUS, fprintf(LogFp,"program address phase completed\n"));

    /* address still has bit 8 zero, so OK here */
    IO_WRITE(PI_FLASH_CTRL_REG,0x80108800 | (enableIntr*PI_FLASH_CTRL_INTR)
        |PI_CTRL_DEV_SHIFT(device));
    POLL_CTRL_BUSY_TIMEOUT;
    __FLASH_VERIFY_INT;
    _TRACE(DSTATUS, fprintf(LogFp,"page programmed\n"));

    return statusRead(0,device,piStatBuffer,enableIntr);
}


/* because status is 0x80 command to flash, statusReadAddr
   is constrained to the first 256B of chosen buffer.
   Also, the statusReadAddr must be 4 byte aligned.
*/
int statusRead(u32 statusReadAddr,u32 dev,u32 buffer, int enableIntr)
{
    int ret;

    /* paranoid - take care of case where enableIntr "true" is > 1 */
    if(enableIntr)
        enableIntr = 1;
    else
        enableIntr = 0;

    if(buffer>1 || dev>3 || statusReadAddr>252 || statusReadAddr&3)
        return -1;

    IO_WRITE(PI_FLASH_ADDR_REG,statusReadAddr);
    IO_WRITE(PI_FLASH_CTRL_REG, 0x90700001 |
             PI_CTRL_DEV_SHIFT(dev)  |
             PI_CTRL_BUF_SHIFT(buffer) |
             (enableIntr*PI_FLASH_CTRL_INTR));
    POLL_CTRL_BUSY_TIMEOUT;
    __FLASH_VERIFY_INT;

    if(buffer==0)
        ret = IO_READ(PI_BUFFER_0_START+statusReadAddr);
    else
        ret = IO_READ(PI_BUFFER_1_START+statusReadAddr);

    return (ret>>24)&0xff;
}


/*
 * addr must be 512B aligned and the entire page is read.
 * The read request to flash (command 0x00) will always
 * request the entire 528B page. The first 512B are placed
 * into the buf array. If oob is non-null the OOB data
 * will be copied there. Endian conversion is done so
 * the data alignment in buf is the same as in the piBuffer.
 *
 * return values:
 *    DRIVER_ECC_DBL_BITERR: bad flash data, ecc double-bit error
 *    DRIVER_ERROR:          bad args
 *    DRIVER_ECC_NO_ACTION:  flash data ok, no ecc action
 *    DRIVER_ECC_SGL_BITERR: flash data ok, single bit ecc error corrected
 */
int readFullPage(
    u32 piBuffer,
    u32 dev,
    u32 addr, /* must be 512B aligned */
    uint eccOn,
    u8 *buf,
    u8 *oob,
    int bigDevice,
    int enableIntr
    )
{
    u32 flashCtrlCmd,*pw,val;
    int i;
    int retval = DRIVER_ECC_NO_ACTION;

    if(piBuffer>1 || (addr&0x1ff) || buf==NULL)
        return DRIVER_ERROR;

    /* paranoid - take care of case where enableIntr "true" is > 1 */
    if(enableIntr)
        enableIntr = 1;
    else
        enableIntr = 0;

    _TRACE(DSTATUS, fprintf(LogFp,"reading flash page\n"));

    IO_WRITE(PI_FLASH_ADDR_REG,addr);
#ifdef TOSHIBA_FLASH
    flashCtrlCmd = 0x9f008000;
#else
    if(bigDevice){
        flashCtrlCmd = 0x9f008000;
    }
    else{
        flashCtrlCmd = 0x97008000;
    }
#endif
    flashCtrlCmd |= PI_FLASH_PAGE_FULL_SIZE;
    if(eccOn)
        flashCtrlCmd |= PI_FLASH_CTRL_ECC;
    flashCtrlCmd |= PI_CTRL_DEV_SHIFT(dev);
    flashCtrlCmd |= PI_CTRL_BUF_SHIFT(piBuffer);
    flashCtrlCmd |= enableIntr*PI_FLASH_CTRL_INTR;

    IO_WRITE(PI_FLASH_CTRL_REG,flashCtrlCmd);
    POLL_CTRL_BUSY_TIMEOUT;

    /* check ecc errors */
    if(eccOn){
        val = IO_READ(PI_FLASH_CTRL_REG);
        if( (val & PI_FLASH_CTRL_SBERR) && (val & PI_FLASH_CTRL_DBERR)){
            retval = DRIVER_ECC_SGL_DBL_BITERR;
        }
        else if(val & PI_FLASH_CTRL_SBERR){
            retval = DRIVER_ECC_SGL_BITERR;
        }
        else if(val & PI_FLASH_CTRL_DBERR){
            retval = DRIVER_ECC_DBL_BITERR;
        }
    }

    /* read back from pi buffer into buf */
    pw = (u32 *)buf;
    for(i=0;i<PI_FLASH_PAGE_DATA_SIZE;i+=4){
        val = IO_READ(PI_BUFFER_0_START+piBuffer*512+i);
        /* printf(" %x %x\n",val,H2BE4(val)); */
        pw[i>>2] = H2BE4(val);
    }

    if(oob){
        pw = (u32 *)oob;
        for(i=0;i<PI_FLASH_OOB_SIZE;i+=4){
            pw[i>>2] = H2BE4(IO_READ(PI_BUFFER_0_OOB_START +
                                     piBuffer*PI_FLASH_OOB_SIZE+i)); 
        }
    }    

    return retval;
}


/*
 * addr must be 512B aligned and the second half of the data
 * in the page is read (the full OOB may be read).
 * The read request to flash (command 0x00) will always
 * request 256+16 bytes from the page. The 256B data is placed
 * into the buf array. If oob is non-null the OOB data
 * will be copied there. Endian conversion is done so
 * the data alignment in buf is the same as in the piBuffer.
 *
 * return values:
 *    DRIVER_ECC_DBL_BITERR: bad flash data, ecc double-bit error
 *    DRIVER_ERROR:          bad args
 *    DRIVER_ECC_NO_ACTION:  flash data ok, no ecc action
 *    DRIVER_ECC_SGL_BITERR: flash data ok, single bit ecc error corrected
 */
int readSecondHalfPage(
    u32 piBuffer,
    u32 dev,
    u32 addr, /* must be 512B aligned */
    uint eccOn,
    u8 *buf,
    u8 *oob,
    int bigDevice,
    int enableIntr
    )
{
    u32 flashCtrlCmd,*pw,val;
    int i;
    int retval = DRIVER_ECC_NO_ACTION;

    if(piBuffer>1 || (addr&0x1ff) || buf==NULL)
        return DRIVER_ERROR;

    /* paranoid - take care of case where enableIntr "true" is > 1 */
    if(enableIntr)
        enableIntr = 1;
    else
        enableIntr = 0;

    _TRACE(DSTATUS, fprintf(LogFp,"reading flash page\n"));

    IO_WRITE(PI_FLASH_ADDR_REG,addr+PI_FLASH_PAGE_DATA_SIZE/2);
#ifdef TOSHIBA_FLASH
    flashCtrlCmd = 0x9f008000;
#else
    if(bigDevice){
        flashCtrlCmd = 0x9f008000;
    }
    else{
        flashCtrlCmd = 0x97008000;
    }
#endif
    flashCtrlCmd |= PI_FLASH_PAGE_FULL_SIZE-PI_FLASH_PAGE_DATA_SIZE/2;
    if(eccOn)
        flashCtrlCmd |= PI_FLASH_CTRL_ECC;
    flashCtrlCmd |= PI_CTRL_DEV_SHIFT(dev);
    flashCtrlCmd |= PI_CTRL_BUF_SHIFT(piBuffer);
    flashCtrlCmd |= enableIntr*PI_FLASH_CTRL_INTR;

    IO_WRITE(PI_FLASH_CTRL_REG,flashCtrlCmd);
    POLL_CTRL_BUSY_TIMEOUT;

    /* check ecc errors */
    if(eccOn){
        val = IO_READ(PI_FLASH_CTRL_REG);

        if( (val & PI_FLASH_CTRL_SBERR) && (val & PI_FLASH_CTRL_DBERR)){
            retval = DRIVER_ECC_SGL_DBL_BITERR;
        }
        else if(val & PI_FLASH_CTRL_SBERR){
            retval = DRIVER_ECC_SGL_BITERR;
        }
        else if(val & PI_FLASH_CTRL_DBERR){
            retval = DRIVER_ECC_DBL_BITERR;
        }
    }

    /* read back from pi buffer into buf */
    pw = (u32 *)buf;
    for(i=0;i<PI_FLASH_PAGE_DATA_SIZE/2;i+=4){
        val = IO_READ(PI_BUFFER_0_START+piBuffer*512+
                      PI_FLASH_PAGE_DATA_SIZE/2+i);
        /* printf(" %x %x\n",val,H2BE4(val)); */
        pw[i>>2] = H2BE4(val);
    }

    if(oob){
        pw = (u32 *)oob;
        for(i=0;i<PI_FLASH_OOB_SIZE;i+=4){
            pw[i>>2] = H2BE4(IO_READ(PI_BUFFER_0_OOB_START +
                                     piBuffer*PI_FLASH_OOB_SIZE+i)); 
        }
    }    

    return retval;
}



/*
   no ECC.
   must start in data region (not OOB).
   can extend into OOB region (?).
   buf gets result from both data and OOB.
*/
int readPartialPage(
    u32 piBuffer,
    u32 dev,
    u32 addr,
    u32 bytes,
    u8 *buf,
    int bigDevice,
    int enableIntr
    )
{
    /* use the 0x00 command and PI_FLASH_ADDR_REG or'ing */
    u32 flashCtrlCmd,*pw,val;
    int i;

    if(piBuffer>1 || buf==NULL || 
       (bytes>(PI_FLASH_PAGE_FULL_SIZE-(addr&0x1ff))))
        return -1;

    if(bytes==0)
        return 0;

    /* paranoid - take care of case where enableIntr "true" is > 1 */
    if(enableIntr)
        enableIntr = 1;
    else
        enableIntr = 0;

    IO_WRITE(PI_FLASH_ADDR_REG,addr);
#ifdef TOSHIBA_FLASH
    flashCtrlCmd = 0x9f008000;
#else
    if(bigDevice){
        flashCtrlCmd = 0x9f008000;
    }
    else{
        flashCtrlCmd = 0x97008000;
    }
#endif
    flashCtrlCmd |= bytes;
    flashCtrlCmd |= PI_CTRL_DEV_SHIFT(dev);
    flashCtrlCmd |= PI_CTRL_BUF_SHIFT(piBuffer);
    flashCtrlCmd |= enableIntr*PI_FLASH_CTRL_INTR;

    IO_WRITE(PI_FLASH_CTRL_REG,flashCtrlCmd);
    POLL_CTRL_BUSY_TIMEOUT;
    __FLASH_VERIFY_INT;

    /* only addressing into buffer at this point */
    addr&=0x1ff;

    /* read non-aligned bytes if needed */
    if(addr&3){
        if(addr<PI_FLASH_PAGE_DATA_SIZE){
            /* starting in data region */
            val = IO_READ(
                PI_BUFFER_0_START+piBuffer*PI_FLASH_PAGE_DATA_SIZE+
                (addr&0x1fc));
        }
        else{
            /* starting in OOB region */
            val = IO_READ(PI_BUFFER_0_OOB_START+piBuffer*PI_FLASH_OOB_SIZE+
                          ((addr-PI_FLASH_PAGE_DATA_SIZE)&0x1fc));
        }
        /* write bytes to buf */
        val = H2LE4(val);
        for(i=3-(addr&3);i>=0;i--){
            *(buf++)=(val>>(i*8))&0xff;
            if((--bytes)==0)
                return 0;
        }
        addr=(addr&0x1fc)+4;
    }

    /* read till all bytes done or OOB boundary reached */
    while(bytes && addr<PI_FLASH_PAGE_DATA_SIZE){
        val = IO_READ(PI_BUFFER_0_START+piBuffer*PI_FLASH_PAGE_DATA_SIZE+addr);
        if(bytes>=4){
            *((u32 *)buf) = H2BE4(val);
            bytes-=4;
            if(bytes==0)
                return 0;
            buf+=4;
            addr+=4;
        }
        else{
            val = H2LE4(val);
            for(i=0;i<bytes;i++){
                *(buf++)=(val>>((3-i)*8))&0xff;
            }
            return 0;
        }

    }

    /* if bytes still to be read, must be in OOB, so read */
    addr-=PI_FLASH_PAGE_DATA_SIZE;
    while(bytes){
        val = IO_READ(PI_BUFFER_0_OOB_START+piBuffer*PI_FLASH_OOB_SIZE+addr);
        if(bytes>=4){
            *((u32 *)buf) = H2BE4(val);
            bytes-=4;
            if(bytes==0)
                return 0;
            buf+=4;
            addr+=4;
        }
        else{
            val = H2LE4(val);
            for(i=0;i<bytes;i++){
                *(buf++)=(val>>((3-i)*8))&0xff;
            }
            return 0;
        }
    }

    /* should not be able to reach here */
    return -1;

}


/*
 * no ECC.
 * must start in OOB region (not data).
 * buf gets result from OOB only.
 * NOTE: because PI_DEV_ADDR[8] is or'd with the
 *   PI_FLASH_CTRL CMD bits, only the first 256B
 *   of pi buffer 0 or 1 may be used. Otherwise,
 *   the 0x50 command would actually be issued as 0x51
 */
int readPartialPageOob(
    u32 piBuffer,
    u32 dev,
    u32 addr,
    u32 bytes,
    u8 *buf,
    int bigDevice,
    int enableIntr
    )
{
    /* use the 0x50 command and PI_FLASH_ADDR_REG or'ing */
    u32 flashCtrlCmd,*pw,val;
    int i;

    if(piBuffer>1 || buf==NULL || bytes > PI_FLASH_OOB_SIZE ||
        ((addr % PI_FLASH_PAGE_DATA_SIZE) > 256 - bytes))
        return -1;

    if(bytes==0)
        return 0;

    /* paranoid - take care of case where enableIntr "true" is > 1 */
    if(enableIntr)
        enableIntr = 1;
    else
        enableIntr = 0;

    IO_WRITE(PI_FLASH_ADDR_REG,addr);
#ifdef TOSHIBA_FLASH
    flashCtrlCmd = 0x9f508000;
#else
    if(bigDevice){
        flashCtrlCmd = 0x9f508000;
    }
    else{
        flashCtrlCmd = 0x97508000;
    }
#endif
    flashCtrlCmd |= bytes;
    flashCtrlCmd |= PI_CTRL_DEV_SHIFT(dev);
    flashCtrlCmd |= PI_CTRL_BUF_SHIFT(piBuffer);
    flashCtrlCmd |= enableIntr*PI_FLASH_CTRL_INTR;

    IO_WRITE(PI_FLASH_CTRL_REG,flashCtrlCmd);
    POLL_CTRL_BUSY_TIMEOUT;
    __FLASH_VERIFY_INT;

    /* only addressing in specified pi buffer */
    addr&=0x1ff;

    /* read non-aligned bytes if needed */
    if(addr&3){
        /*cmd 50 OOB data will be in data region of pi buf */
        val = IO_READ(
            PI_BUFFER_0_START+piBuffer*PI_FLASH_PAGE_DATA_SIZE+
            (addr&0x1fc));

        /* write bytes to buf */
        val = H2LE4(val);
        for(i=3-(addr&3);i>=0;i--){
            *(buf++)=(val>>(i*8))&0xff;
            if((--bytes)==0)
                return 0;
        }
        addr=(addr&0x1fc)+4;
    }

    /* read remaning bytes */
    while(bytes){
        val = IO_READ(PI_BUFFER_0_START+piBuffer*PI_FLASH_PAGE_DATA_SIZE+addr);
        if(bytes>=4){
            *((u32 *)buf) = H2BE4(val);
            bytes-=4;
            if(bytes==0)
                return 0;
            buf+=4;
            addr+=4;
        }
        else{
            val = H2LE4(val);
            for(i=0;i<bytes;i++){
                *(buf++)=(val>>((3-i)*8))&0xff;
            }
            return 0;
        }

    }

    /* should not be able to reach here */
    return -1;

}


#define DBG_flashCheckIntr 0

/*
  Assume the FLASH controller is already not busy.
*/
int flashCheckClearIntr()
{
    u32 io;
    u32 ints, minte, mintem;
    static char msgt[] = "flashCheckClearIntr:  %s:  ints=%08x  MI_INTR_EMASK_REG=%08x  MI_EINTR_REG=%08x\n";

    io = IO_READ(PI_FLASH_CTRL_REG);
    if((io&PI_FLASH_CTRL_BUSY) || !(io&PI_FLASH_CTRL_INTR)) {
        printf("flashCheckClearIntr: busy on or intr off.  PI_FLASH_CTRL_REG=%08x\n", io);
        fflush(NULL);
        return FAIL;
    }

    /* check mi int and int1 */
    ints   = CHECK_INTERRUPT;
    minte  = IO_READ(MI_EINTR_REG);
    mintem = IO_READ(MI_INTR_EMASK_REG);

    #if DBG_flashCheckIntr==1
        printf(msgt, "debug 1", ints, mintem, minte);
        fflush(NULL);
    #endif

    if(!(minte&MI_INTR_FLASH)) {
        printf(msgt, "MI_INTR_FLASH is not set", ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }

    if(mintem & MI_INTR_MASK_FLASH) {
        if(!(ints&2)) {
            printf(msgt, "int1 is not set", ints, mintem, minte);
            fflush(NULL);
            return FAIL;
        }
    } else {
        if(ints&2) {
            printf(msgt, "flash int is masked but int1 is set", ints, mintem, minte);
            fflush(NULL);
            return FAIL;
        }
    }

    /* we have the intr bit set, so try clearing */
    IO_WRITE(PI_FLASH_CTRL_REG,0);

    /* read back to check */
    io     = IO_READ(PI_FLASH_CTRL_REG);
    ints   = CHECK_INTERRUPT;
    minte  = IO_READ(MI_EINTR_REG);

    #if DBG_flashCheckIntr==1
        printf(msgt, "debug 2", ints, mintem, minte);
        fflush(NULL);
    #endif

    if(io&(PI_FLASH_CTRL_INTR|PI_FLASH_CTRL_BUSY)) {
        printf("flashCheckClearIntr: busy or intr on after clear.  PI_FLASH_CTRL_REG=%08x\n", io);
        fflush(NULL);
        return FAIL;
    }

    /* check MI intrs */
    if(minte&MI_INTR_FLASH) {
        printf(msgt, "MI_INTR_FLASH set after clear", ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }
    if(ints&2) {
        printf(msgt, "int1 set after clear", ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }
    return PASS;
}



int flashCheckNoIntr()
{
    u32 io;
    u32 ints, minte, mintem;
    static char msgt[] = "flashCheckNoIntr:  %s:  ints=%08x  MI_INTR_EMASK_REG=%08x  MI_EINTR_REG=%08x\n";

    io = IO_READ(PI_FLASH_CTRL_REG);
    if((io&PI_FLASH_CTRL_BUSY) || io&PI_FLASH_CTRL_INTR) {
        printf("flashCheckNoIntr: busy or intr on.  PI_FLASH_CTRL_REG=%08x\n", io);
        fflush(NULL);
        return FAIL;
    }

    /* check mi int and int1 */
    ints   = CHECK_INTERRUPT;
    minte  = IO_READ(MI_EINTR_REG);
    mintem = IO_READ(MI_INTR_EMASK_REG);

    #if DBG_flashCheckIntr==1
        printf(msgt, "debug 3", ints, mintem, minte);
        fflush(NULL);
    #endif

    if(minte&MI_INTR_FLASH) {
        printf(msgt, "MI_INTR_FLASH is set", ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }

    if(ints&2) {
        printf(msgt, "flash int is not enabled but int1 is set", ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }

    return PASS;
}



/*
  inputs are as defined in the pi hardware spec:
    dataOffset is the number of 16B chunks from start of pi buffer.
    initVectOffset is same.
    dataSize is also in 16B chunks, but here 0 means 0.
*/
int aesStart(u32 dataOffset,u32 initVectOffset,u32 dataSize,int intEnable, int  hardwareChaining)
{
    u32 aesCmd=PI_AES_CTRL_BASE;

    if(intEnable)
        aesCmd |= PI_AES_CTRL_INTR;



    aesCmd|=PI_AES_DATA_SHIFT(dataOffset);
    if(hardwareChaining){
      aesCmd |= PI_AES_CTRL_HC;
    }
    else{
     aesCmd|=PI_AES_IV_SHIFT(initVectOffset);
    }
    aesCmd|=PI_AES_SIZE_SHIFT(dataSize-1);
    IO_WRITE(PI_AES_CTRL_REG,aesCmd);
    return 0;
}


int getline(char *line,int max,FILE *fp)
{
    if(fgets(line,max,fp)==NULL)
        return -1;
    else
        return strlen(line);
}


/* buf holds 528 bytes */
/* assumes format where a line like:
 *      // page NNN
 * is directly followed by 528 B of data. NNN
 * is the page number (from zero).
 */
int flashFileGetPage(FILE *fp,u32 pageNum,u8 *buf)
{
    static const bytesPerPage = 528*3+10;
    int len,i,tmp;
    u32 searchPage;

    /* get close */
    fseek(fp,pageNum*bytesPerPage,SEEK_SET);

    do{
        len = getline(buf,528,fp);
        if(len==-1){
            return -1;
        }
        if(( buf[0] == buf[1])&&(buf[0] == '/')){
            searchPage = atoi(strrchr(buf,' '));
            if(searchPage>= pageNum)
                break;
        }
    } while(1);

    if(pageNum>searchPage)
        return -1;

    /* fill in buffer with bytes */
    for(i=0;i<528;i++){
        fscanf(fp,"%x",&tmp);
        buf[i]=(unsigned char)tmp;
    }

    return searchPage;
}



int setMemModPresence(int remove)
{
    int ret,i,sk,maxloops=10;
    u32 ints, minte, mintem, mismr;
    u32 minte_orig;
    u32 minte_after_clear;
    u32 ide;
    u32 new_state_ide_mask  = remove ? 0x8008:0x0008;
    u32 new_state_minte_mask = remove ? MI_EINTR_MODULE_REMOVED:0;
    static char msgt[] = "setMemModPresence:  %s:  request==%s  MI_SEC_MODE_REG==%08x  ints=%08x  MI_INTR_EMASK_REG=%08x  MI_EINTR_REG=%08x\n";
    char *request = remove ? "remove":"insert";
    #define DBG_MemModPresence 0


    /* check mi int, int1, and MD trap */
    minte  = IO_READ(MI_EINTR_REG);
    mintem = IO_READ(MI_INTR_EMASK_REG);
    mismr  = IO_READ(MI_SEC_MODE_REG);
    ints   = CHECK_INTERRUPT;

    printf("\n");
    fflush(NULL);

    #if DBG_MemModPresence==1
        printf(msgt, "on entry.", request, mismr, ints, mintem, minte);
        fflush(NULL);
    #endif

    /* clear MD intr */
    if(minte&MI_INTR_MD) {
        IO_WRITE(MI_EINTR_REG,MI_INTR_MD);
        minte = IO_READ(MI_EINTR_REG);
        ints   = CHECK_INTERRUPT;
        #if DBG_MemModPresence==1
            printf(msgt, "after clear MD intr on entry", request, mismr, ints, mintem, minte);
            fflush(NULL);
        #endif
        if(minte&MI_INTR_MD) {
            printf(msgt, "could't clear MI_INTR_MD on entry", request, mismr, ints, mintem, minte);
            fflush(NULL);
            return FAIL;
        }
        if(ints&2) {
            printf(msgt, "int1 wasn't cleared on entry", request, mismr, ints, mintem, minte);
            fflush(NULL);
            return FAIL;
        }
    }

    /* clear trap */
    if(mismr&MI_SEC_MODE_MD_TRAP) {
        IO_WRITE(MI_SEC_MODE_REG, mismr & ~MI_SEC_MODE_MD_TRAP);
        mismr = IO_READ(MI_SEC_MODE_REG);
        #if DBG_MemModPresence==1
            printf(msgt, "after clear MD trap on entry", request, mismr, ints, mintem, minte);
            fflush(NULL);
        #endif
        if(mismr&MI_SEC_MODE_MD_TRAP) {
            printf(msgt, "could't clear MD trap on entry", request, mismr, ints, mintem, minte);
            fflush(NULL);
            return FAIL;
        }
    }

    /* check whether need to change MD state */
    minte_orig = IO_READ(MI_EINTR_REG);
    if((minte_orig&MI_EINTR_MD_STATUS)==new_state_minte_mask) {
        #if DBG_MemModPresence==1
            printf(msgt, "MD insert/remove was already requested value", request, mismr, ints, mintem, minte);
            fflush(NULL);
        #endif
        return PASS; /* already the requested value */
    }

    ide = IO_READ(PI_IDE_CONFIG_REG);
    if(ide&PI_IDE_CONFIG_RESET)
        IO_WRITE(PI_IDE_CONFIG_REG,ide&(~PI_IDE_CONFIG_RESET));

    IO_WRITE(MI_EINTR_REG, MI_INTR_MD); /* clear module state change indicator */
    minte_after_clear = IO_READ(MI_EINTR_REG);

    if (rand()&1) {
        IDE_WRITE(PI_IDE3_MD_ZERO_LIST_PTR,0);
        IDE_WRITE(PI_IDE3_MD_SET_LIST_DATA,new_state_ide_mask);
        IDE_WRITE(PI_IDE3_MD_SET_LIST_DATA,0);
        IDE_WRITE(PI_IDE3_MD_TRIGGER,0);
    } else
        IDE_WRITE(PI_IDE3_MD_PRESENCE,remove?1:0);

    for(i=0; i<maxloops; ++i) {
        minte=IO_READ(MI_EINTR_REG);
        if(i==0||i==(maxloops-1)) {
            /*printf("i==%d, MI_EINTR_REG==%08x\n",i,minte);*/
            fflush(NULL);
        }
        if((minte&MI_INTR_MD)==MI_INTR_MD) {
            _TRACE(DSTATUS,fprintf(LogFp,msgt,"md insert/remove change detected", request, mismr, ints, mintem, minte));
            fflush(NULL);
            break;
        }
    }
    if(i==maxloops) {
        printf("setMemModPresence: expected module state change did not occur.\n"
               "  remove %d\n  minte_orig %08x\n  minte_after_clear %08x\n"
               "  new_state_ide_mask %08x\n  new_state_minte_mask %08x\n  MI_EINTR_REG %08x\n\nsetMemModPresence  "
               , remove, minte_orig, minte_after_clear, new_state_ide_mask, new_state_minte_mask, minte);
        OUTPUT_TEST_PASSFAIL(FAIL);
        fflush(NULL);
        return FAIL;
    }

    if(!((minte&MI_EINTR_MD_STATUS)==new_state_minte_mask)) {
        printf("setMemModPresence: expected module state was not set.\n"
               "  remove %d\n  minte_orig %08x\n  minte_after_clear %08x\n"
               "  new_state_minte_mask %08x  MI_EINTR_REG %0x8\n\nsetMemModPresence  "
               , remove, minte_orig, minte_after_clear, new_state_minte_mask, minte);
        OUTPUT_TEST_PASSFAIL(FAIL);
        fflush(NULL);
        return FAIL;
    }

    /* check mi int, int1, and MD trap */
    ints   = CHECK_INTERRUPT;
    mintem = IO_READ(MI_INTR_EMASK_REG);
    mismr  = IO_READ(MI_SEC_MODE_REG);

    #if DBG_MemModPresence==1
        printf(msgt, "after change MD state", request, mismr, ints, mintem, minte);
        fflush(NULL);
    #endif

    if(!(minte & MI_INTR_MD)) {
        printf(msgt, "MI_INTR_MD is not set", request, mismr, ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }

    if( ( (ints&2) && !(mintem & MI_INTR_MASK_MD)) ||
        (!(ints&2) &&  (mintem & MI_INTR_MASK_MD)) ){
        char *msg = (ints&2) ? "MD int mask is not set but int1 is set" : "int1 is not set";
        printf(msgt, msg, request, mismr, ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }

    sk = mismr & MI_SEC_MODE_MD_TRAP_EN;
    if( ( sk && !(mismr & MI_SEC_MODE_MD_TRAP)) ||
        (!sk &&  (mismr & MI_SEC_MODE_MD_TRAP)) ){
        char *msg = sk ? "SMD trap is not set" : "SMD trap not expected";
        printf(msgt, msg, request, mismr, ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }

    /* clear MD intr */
    IO_WRITE(MI_EINTR_REG,MI_INTR_MD);
    minte  = IO_READ(MI_EINTR_REG);
    mintem = IO_READ(MI_INTR_EMASK_REG);
    mismr  = IO_READ(MI_SEC_MODE_REG);
    ints   = CHECK_INTERRUPT;

    #if DBG_MemModPresence==1
        printf(msgt, "after clear MD intr", request, mismr, ints, mintem, minte);
        fflush(NULL);
    #endif

    if(minte & MI_INTR_MD) {
        printf(msgt, "could't clear MI_INTR_MD", request, mismr, ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }
    if(ints&2) {
        printf(msgt, "int1 wasn't cleared", request, mismr, ints, mintem, minte);
        fflush(NULL);
        return FAIL;
    }

    /* clear trap */
    if(mismr&MI_SEC_MODE_MD_TRAP) {
        IO_WRITE(MI_SEC_MODE_REG, mismr & ~MI_SEC_MODE_MD_TRAP);
        mismr = IO_READ(MI_SEC_MODE_REG);
        #if DBG_MemModPresence==1
            printf(msgt, "after clear MD trap", request, mismr, ints, mintem, minte);
            fflush(NULL);
        #endif
        if(mismr&MI_SEC_MODE_MD_TRAP) {
            printf(msgt, "could't clear MD trap", request, mismr, ints, mintem, minte);
            fflush(NULL);
            return FAIL;
        }
    }

    return PASS;
}


int setMemModPresenceQuick(int remove)
{
    int ret,i,sk,maxloops=10;
    u32 ints, minte, mintem, mismr;
    u32 minte_orig;
    u32 minte_after_clear;
    u32 ide;
    u32 new_state_ide_mask  = remove ? 0x8008:0x0008;
    u32 new_state_minte_mask = remove ? MI_EINTR_MODULE_REMOVED:0;
    char *request = remove ? "remove":"insert";

    /* check whether need to change MD state */
    minte_orig = IO_READ(MI_EINTR_REG);
    if((minte_orig&MI_EINTR_MD_STATUS)==new_state_minte_mask) {
        return PASS; /* already the requested value */
    }

    ide = IO_READ(PI_IDE_CONFIG_REG);
    if(ide&PI_IDE_CONFIG_RESET)
        IO_WRITE(PI_IDE_CONFIG_REG,ide&(~PI_IDE_CONFIG_RESET));

    /* clear module state change indicator */
    IO_WRITE(MI_EINTR_REG, MI_INTR_MD); 
    minte_after_clear = IO_READ(MI_EINTR_REG);

    IDE_WRITE(PI_IDE3_MD_PRESENCE,remove?1:0);

    for(i=0; i<maxloops; ++i) {
        minte=IO_READ(MI_EINTR_REG);
        if((minte&MI_INTR_MD)==MI_INTR_MD) {
            break;
        }
    }
    if(i==maxloops) {
        printf("setMemModPresenceQuick: timeout attempting state change.\n");
        OUTPUT_TEST_PASSFAIL(FAIL);
        fflush(NULL);
        return FAIL;
    }

    if(!((minte&MI_EINTR_MD_STATUS)==new_state_minte_mask)) {
        printf("setMemModPresenceQuick: could not change state.\n");
        OUTPUT_TEST_PASSFAIL(FAIL);
        fflush(NULL);
        return FAIL;
    }

    /* clear MD intr */
    IO_WRITE(MI_EINTR_REG,MI_INTR_MD);

    /* clear trap */
    if(mismr&MI_SEC_MODE_MD_TRAP) {
        IO_WRITE(MI_SEC_MODE_REG, mismr & ~MI_SEC_MODE_MD_TRAP);
        mismr = IO_READ(MI_SEC_MODE_REG);
        if(mismr&MI_SEC_MODE_MD_TRAP) {
            printf("could't clear MD trap\n"); 
            fflush(NULL);
            return FAIL;
        }
    }

    return PASS;
}


int insertMemModule()
{
    return setMemModPresence(0);
}

int removeMemModule()
{
    return setMemModPresence(1);
}


int toggleFlashIntMask(int new_state)
{
    /*  new_state == 0   clr mask bit, fail if not currently set
     *  new_state != 0   set mask bit, fail if not currently clr
    */
    u32 mintme=IO_READ(MI_INTR_EMASK_REG);
    int state = (mintme&MI_INTR_MASK_FLASH) ? 1:0;
    int expected_state = new_state ? 0:1;
    int new_mask  = new_state ? MI_INTR_MASK_SET_FLASH : MI_INTR_MASK_CLR_FLASH;

    if( state != expected_state ) {
        printf("toggleFlashIntMask: expected MI_INTR_MASK_FLASH %s: %08x    ",
                (expected_state ? "set":"clr"), mintme);
        OUTPUT_TEST_PASSFAIL(FAIL);
        fflush(NULL);
        return FAIL;
    }

    IO_WRITE(MI_INTR_EMASK_REG, new_mask);
    return PASS;
}



/*
  addrOffset is offset into ATB buffer region. So, the
  actual address is PI_BUF_ATB+addrOffset. addrOffset
  must be 4 byte aligned.

  wordLow is 4 byte word to be written to address specified
  by addrOffset.

  bits9 holds upper 9 bits of ATB entry at addrOffset
  in its LSBs.
*/
void atbWrite(u32 wordLow,u32 bits9,u32 addrOffset)
{
    IO_WRITE(PI_ATBU_REG,bits9);
    IO_WRITE(PI_ATB_BUFFER_LO_REG+addrOffset,wordLow);
}


void atbRead(u32 *wordLow,u32 *bits9,u32 addrOffset)
{
    u32 addrAligned;

    *wordLow = IO_READ(PI_ATB_BUFFER_LO_REG+addrOffset);

    /* access to the upper bit of two consecutive entries
     * is done with a single read. So, the reads to the
     * PI_BUF_ATBU_READ space must be 8-byte aligned.
     */
    *bits9 = IO_READ(PI_ATB_BUFFER_HI_REG+PI_ATB_BUFFER_OFFSET+(addrOffset&~7));
    if(!(addrOffset&4)){
        *bits9 = (*bits9)>>16;
    }
    *bits9 &= 0x1ff;
}


/*
 * returns:
 *   0 if dma completed normally
 *   1 if dma terminated due to error or timeout
 */
int pollDMA(long long expected_time){   
    long long new_st, old_st;
    u32 error = 0;
    /*POLL_DMA_STATUS;*/
    SIM_TIME(&old_st);
    do{
        SIM_TIME(&new_st);
        if(new_st %10000 == 0){
            error = IO_READ(PI_ERROR_REG);
        }
    }while( 
        (IO_READ(PI_STATUS_REG)&PI_STATUS_DMA_BUSY) &&
        ((new_st - old_st)< expected_time) &&
        ((error & 0x00000003)==0) 
        );
    printf("dma stopped at %lld\n",new_st);
    printf("time taken = %lld\n", new_st - old_st);
    if( (IO_READ(PI_STATUS_REG)&PI_STATUS_DMA_BUSY)==0 && (error&3)==0 ){
        printf("dma finished!\n");
        return 0;
    }
    else if((IO_READ(PI_STATUS_REG)&PI_STATUS_DMA_BUSY)==0 && (error&3)!=0 ){
        printf("dma finished but error set!\n");
        return 1;
    }
    return 2;
}
    

int piCheckIntClear()
{
    /* insure int clear on MI */
    if(MI_PI_INTR_IS_SET){
        _TRACE(DERROR, fprintf(LogFp,"MI PI int should not be set.\n"));
        return FAIL;
    }

    /* insure int clear at cpu */
    if(PI_CPU_INTR_IS_SET){
        _TRACE(DERROR, fprintf(LogFp,"PI cpu int should not be set.\n"));
        return FAIL;
    }

    return PASS;
}

/* dram_addr is first byte of tranfer */
int checkDramStartGuardBand(u32 dram_addr)
{
    int j;
    u32 i;
    u32 v;

    for(i=(dram_addr&(~0xf));i<dram_addr;i+=4){
        v = IO_READ(i);
        for(j=3;j>=MAX(0,4-(int)(dram_addr-i));j--){
            if(((v>>(8*j))&0xff) != (((PI_DMA_DRAM_GUARD>>(8*j))&0xff)) ){
                printf("Gaurd band error at start! (%08x)\n",v);
                return 1;
            }
        }
    }
    return 0;
}

/* dram_addr is first byte to check */
int checkDramEndGuardBand(u32 dram_addr)
{
    int j;
    u32 i;
    u32 v;

    if((dram_addr&0xf) == 0)
        return 0;

    for(i=(dram_addr&(~3));i<(dram_addr|0xf);i+=4){
        v = IO_READ(i);
        for(j=0;j<MIN(4,(i+4)-dram_addr);j++){
            if(((v>>(8*j))&0xff) != (((PI_DMA_DRAM_GUARD>>(8*j))&0xff)) ){
                printf("Gaurd band error at end! (%08x)\n",v);
                return 1;
            }
        }
    }
    return 0;
}

void goIntoSecureMode(){
  IO_READ(MI_SEC_MODE_REG);
  IO_READ(BOOT_RAM_LO_START);
}

void exitSecureModeGrantAccess(){
  u32 error;
  IO_WRITE(PI_ACCESS_REG, 0x000000ff);
 /*
  * Exit secure mode
  */
  error = IO_READ(MI_SEC_MODE_REG);
  error = error & 0x42;
  IO_WRITE(MI_SEC_MODE_REG, error);
}

/* use this to read secure mode register while in non secure mode */
u32 getSecureModeRegister(){
  u32 result;
  goIntoSecureMode();
  result = IO_READ(MI_SEC_MODE_REG);
  MI_SFATAL_RESET;
  exitSecureModeGrantAccess();
  return result;
}


int checkMIErrorIntrSet(){
  int result;
  if((IO_READ(MI_EINTR_REG) & 0x0000200)!= 0x0){
    return 1;
  }
  else{
    return 0;
  }
}

int checkCPUErrorIntrSet()
{
    
    if(PI_CPU_EINTR_IS_SET){
        return 1;
    }

    return 0;
}

int resetSFATAL(){
  goIntoSecureMode();
  MI_SFATAL_RESET;
  exitSecureModeGrantAccess();
}