rdramreg.tst
3.24 KB
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//****************************************************************************
//
// File: rdramreg.tst
// Check ability to read RDRAM registers
//
// $Revision: 1.2 $
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// q - Quit testing and shutdown verilog
// server
//
//****************************************************************************
//****************************************************************************
// Configure RDRAMs: 6 MB (MUST MATCH VERILOG BUILD!)
// If Verilog only contains 4MB RDRAM, then change 3 argument to 00000004
//t 0000 00000001 00000006 00000000 00000000
// Haishan Change to make it work on 4MB system
t 0000 00000001 00000004 00000000 00000000
// Set RDRAM register mode on MI
t 0102 04300000 00002000 00000000 00000000
// Check MI mode register
t 0108 04300000 00000200 00000380 00000000
//****************************************************************************
// Read registers from rdram 0
// DeviceType register
t 0108 03f00000 b4190000 f4ff00ff 00000000
// DeviceId register
t 0108 03f00004 00000000 f840ff40 00000000
// Delay register
t 0108 03f00008 2b3b1a0b 3fff1fff 00000000
// Mode register
t 0108 03f0000c c2c0c0c0 ffc0c0c0 00000000
// RefRow register
t 0108 03f00014 00000000 fe080300 00000000
// MinInterval register
t 0108 03f0001c 0040c0e0 e0e0e0ff 00000000
// AddressSelect register
t 0108 03f00020 00000000 fe030000 00000000
// DeviceManufacture register
// t 0108 03f00024 00000000 ffffffff 00000000
t 0108 03f00024 01000500 ffffffff 00000000
// Row register
t 0108 03f00200 00000000 fe03fe03 00000000
//****************************************************************************
// Read registers from rdram 1
// DeviceType register
t 0108 03f00400 b4190000 f4ff00ff 00000000
// DeviceId register
t 0108 03f00404 00000000 f840ff40 08000000
// Delay register
t 0108 03f00408 2b3b1a0b 3fff1fff 00000000
// Mode register
t 0108 03f0040c c2c0c0c0 ffc0c0c0 00000000
// RefRow register
t 0108 03f00414 00000000 fe080300 00000000
// MinInterval register
t 0108 03f0041c 0040c0e0 e0e0e0ff 00000000
// AddressSelect register
t 0108 03f00420 00000000 fe030000 00000000
// DeviceManufacture register
// t 0108 03f00424 00000000 ffffffff 00000000
t 0108 03f00424 01000500 ffffffff 00000000
// Row register
t 0108 03f00600 00000000 fe03fe03 00000000
//****************************************************************************
// Clear RDRAM register mode on MI
t 0102 04300000 00001000 00000000 00000000
// Check MI mode register
t 0108 04300000 00000000 00000380 00000000
// RDRAM 0 Mode register
t 0108 03f0000c 00000000 ffffffff 00000000
// RDRAM 0 MinInterval register
t 0108 03f0001c 00000000 ffffffff 00000000
// RDRAM 1 Mode register
t 0108 03f0040c 00000000 ffffffff 00000000
// RDRAM 1 MinInterval register
t 0108 03f0041c 00000000 ffffffff 00000000
//****************************************************************************
// QUIT
//****************************************************************************
q