initialize.c
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#include <R4300.h>
#include <rcp.h>
#include <ramrom.h>
#include "osint.h"
#include "piint.h"
#include "rdb.h"
#ifdef BBPLAYER
#include <bcp.h>
#include "bbint.h"
#include "bbdebug.h"
#endif
u8 __osBbLibVersion[] = VERSION;
typedef struct {
unsigned int inst1; /* lui k0,XXXX */
unsigned int inst2; /* addiu k0,k0,XXXX */
unsigned int inst3; /* jr k0 */
unsigned int inst4; /* nop */
} __osExceptionVector;
#define ASIC_STATUS 0x05000508
u64 osClockRate = 62500000LL;
int osViClock = VI_NTSC_CLOCK; /* Video clock rate (default is NTSC) */
s32 __osShutdown = 0; /* 1 = pre-NMI interrupt has occured */
u32 __osShutdownTime = 0;
OSIntMask __OSGlobalIntMask = OS_IM_ALL;
#ifdef _FINALROM
s32 __osFinalrom;
#else
s32 __kmc_pt_mode;
void *__printfunc = NULL;
#endif
#if 0
#ifndef _FINALROM
static void ptstart(void)
{
}
#endif
#endif
void __createSpeedParam(void)
{
/* for domain1 */
__Dom1SpeedParam.type = DEVICE_TYPE_INIT;
__Dom1SpeedParam.latency = (u8)IO_READ(PI_BSD_DOM1_LAT_REG);
__Dom1SpeedParam.pulse = (u8)IO_READ(PI_BSD_DOM1_PWD_REG);
__Dom1SpeedParam.pageSize = (u8)IO_READ(PI_BSD_DOM1_PGS_REG);
__Dom1SpeedParam.relDuration = (u8)IO_READ(PI_BSD_DOM1_RLS_REG);
/* for domain2 */
__Dom2SpeedParam.type = DEVICE_TYPE_INIT;
__Dom2SpeedParam.latency = (u8)IO_READ(PI_BSD_DOM2_LAT_REG);
__Dom2SpeedParam.pulse = (u8)IO_READ(PI_BSD_DOM2_PWD_REG);
__Dom2SpeedParam.pageSize = (u8)IO_READ(PI_BSD_DOM2_PGS_REG);
__Dom2SpeedParam.relDuration = (u8)IO_READ(PI_BSD_DOM2_RLS_REG);
}
void
__osInitialize_common(void)
{
u32 pifdata;
/*
* Turn on FS bit to flush denormalized number to zero;
* enable "invalid operation" faulting to catch generation of NaNs.
*/
#ifdef _FINALROM
__osFinalrom = 1;
#endif
__osSetSR(__osGetSR() | SR_CU1);
__osSetFpcCsr(FPCSR_FS | FPCSR_EV);
/* Set no watch exception (adr:0x04900000,R:0,W:0) */
__osSetWatchLo(0x04900000);
#ifndef _HW_VERSION_1
/* send flag to PIF to enable NMI */
#ifdef BBPLAYER
/* probe MI_EINTR_MASK register */
{
u32 x, y;
IO_WRITE(MI_INTR_EMASK_REG, MI_INTR_MASK_SET_IDE|MI_INTR_MASK_SET_FLASH);
x = IO_READ(MI_INTR_EMASK_REG);
IO_WRITE(MI_INTR_EMASK_REG, MI_INTR_MASK_CLR_IDE|MI_INTR_MASK_CLR_FLASH);
y = IO_READ(MI_INTR_EMASK_REG);
__osBbIsBb = ((x&(MI_INTR_MASK_FLASH|MI_INTR_MASK_IDE)) ==
(MI_INTR_MASK_FLASH|MI_INTR_MASK_IDE) &&
(y&(MI_INTR_MASK_FLASH|MI_INTR_MASK_IDE)) == 0);
/* check for rev 1.1 version of BCP */
if (__osBbIsBb && (IO_READ(PI_GPIO_REG) & PI_ID_BOARD_REV_MASK))
__osBbIsBb = 2;
}
/* XXXwheeler: temporarily whack in some values that the boot code would
* normally set up */
if (__osBbIsBb) {
osTvType = OS_TV_NTSC; /* 0 = PAL, 1 = NTSC, 2 = MPAL */
osRomType = 0; /* Bulk or cartridge ROM. 0=cartridge 1=bulk */
osResetType = 0; /* 0 = cold reset, 1 = NMI */
osVersion = 1;
}
if (!__osBbIsBb) {
#endif
while(__osSiRawReadIo(PIF_RAM_START+0x3c, &pifdata));
while (__osSiRawWriteIo(PIF_RAM_START+0x3c, pifdata|8));
#ifdef BBPLAYER
}
#endif
#endif
*(__osExceptionVector *)UT_VEC =
*(__osExceptionVector *)__osExceptionPreamble;
*(__osExceptionVector *)XUT_VEC =
*(__osExceptionVector *)__osExceptionPreamble;
*(__osExceptionVector *)ECC_VEC =
*(__osExceptionVector *)__osExceptionPreamble;
*(__osExceptionVector *)E_VEC =
*(__osExceptionVector *)__osExceptionPreamble;
osWritebackDCache((void*)UT_VEC,
E_VEC - UT_VEC + sizeof(__osExceptionVector));
osInvalICache((void*)UT_VEC,
E_VEC - UT_VEC + sizeof(__osExceptionVector));
/* Store current PI value to global variables */
__createSpeedParam();
/*
* TLB $B$N=i4|2=$r$7$F$*$/!#EE8;N)$A>e$2;~$OITDjCM$,F~$C$F$$$k(B
* $B$3$H$,$"$k$?$a!"=i4|2=$r$7$F$*$+$J$$$H(B TLB $B;HMQ;~$K8mF0:n$r(B
* $B$9$k2DG=@-$,$"$k!#(B
*/
osUnmapTLBAll();
/* set TLB for the debug port */
/* Global, 4K page, even-page only */
osMapTLBRdb();
/* *((vu32 *) RDB_WRITE_INTR_REG) = 0;
*((vu32 *) RDB_READ_INTR_REG) = 0; */
/* Set clock rate */
osClockRate = (osClockRate * 3) / 4;
/* zero out the NMI buffer if cold reset */
if (osResetType == 0) {
bzero(osAppNMIBuffer, OS_APP_NMI_BUFSIZE);
}
/* set video clock based on osTvType */
if (osTvType == OS_TV_PAL)
osViClock = VI_PAL_CLOCK;
else if (osTvType == OS_TV_MPAL)
osViClock = VI_MPAL_CLOCK;
else /* for now, we assume that it's NTSC */
osViClock = VI_NTSC_CLOCK;
/* check PreNMI */
if (__osGetCause() & CAUSE_IP5)
while(1);
#ifdef BBPLAYER
if (!__osBbIsBb) {
__osBbEepromSize = 512;
__osBbPakSize = 32*1024;
__osBbFlashSize = 128*1024;
__osBbEepromAddress = (void*)0x80400000-512;
__osBbPakAddress[0] = (void*)0x80400000-32*1024-512;
__osBbPakAddress[1] = 0;
__osBbPakAddress[2] = 0;
__osBbPakAddress[3] = 0;
__osBbFlashAddress = (void*)0x80400000-128*1024;
/* Flash and Sram should be mutually exclusive */
__osBbSramSize = __osBbFlashSize;
__osBbSramAddress = __osBbFlashAddress;
}
if (__osBbIsBb) {
/* miscellaneous BB initialization (temporary) */
/* turn off reset on IDE */
IO_WRITE(PI_IDE_CONFIG_REG, (IO_READ(PI_IDE_CONFIG_REG)&~PI_IDE_CONFIG_RESET));
/* unblock the ide interrupt */
IO_WRITE(MI_INTR_EMASK_REG, MI_INTR_MASK_SET_IDE);
/* Set button enable */
IO_WRITE(SI_CTRL_REG, 0);
IO_WRITE(SI_CONFIG_REG, (IO_READ(SI_CONFIG_REG) & ~SI_CONFIG_JC_DIV_MASK)
| (47 << SI_CONFIG_JC_DIV_SHIFT)
| SI_CONFIG_BUT_ENA);
}
#endif
/* XXX This cannot be done before the AV PLL is stable and
* AV is out of reset
*/
/* set ai dma on */
IO_WRITE(AI_CONTROL_REG, AI_CONTROL_DMA_ON);
IO_WRITE(AI_DACRATE_REG, AI_MAX_DAC_RATE-1);
IO_WRITE(AI_BITRATE_REG, AI_MAX_BIT_RATE-1);
}
/* $B%G%P%C%,$N<oN`$r<+F0H=Dj$7$F!"5!<o$4$H$N=i4|2=$r9T$&(B */
void __osInitialize_autodetect(void)
{
#ifndef _FINALROM
extern int __checkHardware_kmc(void), __checkHardware_isv(void);
extern int __checkHardware_msp(void);
if (0&&__checkHardware_msp()){
__osInitialize_msp();
#ifdef BBPLAYER
}else if (!__osBbIsBb && __checkHardware_kmc()){
#else
}else if (__checkHardware_kmc()){
#endif
__osInitialize_kmc();
}else if (0&&__checkHardware_isv()){
__osInitialize_isv();
}else{
__osInitialize_emu();
}
#endif
}