at.h
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/*
* at.h: types, macros, etc. for Attribute Double Buffer
*
* The Csim actually delays each attribute in a pipeline, where
* the Verilog uses latches with some state machine to time the
* changing of attributes between primitives.
*
* 9/6/94 RJM
*/
#ifndef ATTR_UNIT_INCLD
#define ATTR_UNIT_INCLD
#include "ints.h"
typedef enum {
DELAY_1, DELAY_2, DELAY_3, DELAY_4,
DELAY_5, DELAY_6, DELAY_7, DELAY_8,
DELAY_9, DELAY_10, DELAY_11, DELAY_12,
DELAY_13, DELAY_14, DELAY_15, DELAY_16,
DELAY_17, DELAY_18, DELAY_19, DELAY_20,
DELAY_21, DELAY_22, DELAY_23, DELAY_24,
DELAY_25, DELAY_26, DELAY_27, DELAY_28,
DELAY_29, DELAY_30, DELAY_31, DELAY_32,
DELAY_33, DELAY_34, DELAY_35, DELAY_36,
DELAY_37, DELAY_38, DELAY_39, DELAY_40,
DELAY_41, DELAY_42, DELAY_43, DELAY_44,
DELAY_45, DELAY_46, DELAY_47, DELAY_48,
DELAY_49, DELAY_50, DELAY_51, DELAY_52
} DelayConstants;
/*
* Number of relative delays (from time latched) for various attributes,
* int and frac are lined up at input to pipe.
*
* Delays don't include: one delay to line up int/frac parts of word,
* one delay from output of pipe to module output register.
*
* Delays for S/T/W/L include 2 delays for worst case (!tlut_en).
*/
#define ST_DXR_INT_DLY (DELAY_23+5)
#define ST_DXG_INT_DLY (DELAY_23+5)
#define ST_DXB_INT_DLY (DELAY_25+5)
#define ST_DXA_INT_DLY (DELAY_25+5)
#define ST_DXZ_INT_DLY (DELAY_24+5)
#define ST_DXS_INT_DLY DELAY_17
#define ST_DXT_INT_DLY DELAY_17
#define ST_DXW_INT_DLY DELAY_13
#define ST_DYR_INT_DLY (DELAY_14+5)
#define ST_DYG_INT_DLY (DELAY_14+5)
#define ST_DYB_INT_DLY (DELAY_16+5)
#define ST_DYA_INT_DLY (DELAY_16+5)
#define ST_DYZ_INT_DLY (DELAY_15+5)
/* New added for LOD fix */
#define ST_DYS_INT_DLY DELAY_5 /* should only need single buffering on these */
#define ST_DYT_INT_DLY DELAY_5
#define ST_DYW_INT_DLY DELAY_5
#define ST_SPAN_DLY (DELAY_40+5)
/* added 1 to match verilog for now */
#define REL_SYNC_PIPE_DLY (DELAY_43+5)
#define REL_SYNC_FULL_DLY (DELAY_43+5)
#define REL_SYNC_TILE_DLY (DELAY_28+5)
#define REL_SYNC_LOAD_DLY (DELAY_18+5)
#define ATOMIC_PRIM_COUNT (37+5)
#define PRIM_COLOR_DLY (DELAY_34+5) /* prim level frac, RGB */
#define PRIM_COLOR_ML (DELAY_21+5) /* if tlut_en, min level */
#define PRIM_DEPTH_DLY (DELAY_36+5) /* MS portion */
#define PRIM_DEPTH_LS_DLY (DELAY_35+5) /* LS portion */
#define SIGN_DLY DELAY_18
#define EW_MAJOR_SIGN_DLY DELAY_2
#define EW_OFFSET_SIGN_DLY DELAY_15
#define LOAD_DLY DELAY_20 /* was 23, changed to match verilog */
#define EW_SCISSOR_LOAD_DLY DELAY_2
#define EW_IMAGE_LOAD_DLY 0
#define EW_STALL_LOAD_DLY DELAY_12
#define EW_OFFSET_LOAD_DLY DELAY_16
#define ST_LOAD_DLY DELAY_20
#define SHIFT_COORD_DLY (DELAY_22+5)
#define LEVEL_DLY (DELAY_19+5)
#define TILE_DLY (DELAY_19+5)
#define LEFT_DLY (DELAY_39+5)
#define EW_MAJOR_LEFT_DLY DELAY_3
#define EW_MINOR_LEFT_DLY DELAY_12
#define EW_OFFSET_LEFT_DLY DELAY_16
#define CV_LEFT_DLY DELAY_12
#define ST_R_LEFT_DLY (DELAY_33+5)
#define ST_G_LEFT_DLY (DELAY_33+5)
#define ST_B_LEFT_DLY (DELAY_33+5)
#define ST_A_LEFT_DLY (DELAY_33+5)
#define ST_Z_LEFT_DLY (DELAY_35+5)
#define ST_S_LEFT_DLY DELAY_20
#define ST_T_LEFT_DLY DELAY_20
#define ST_W_LEFT_DLY DELAY_18
/*
* Memory structure for Attribute Double Buffer
*/
typedef struct
{
/* required by C-sim */
char *label; /* label must be first */
char **argv;
int argc;
int gclk_old;
int clk_old;
/* I n p u t S i g n a l s */
int gclk;
int clk;
int reset_l;
int cs_st_prim;
int cs_st_attr;
int cs_cmd; /* [5:0] */
int64 cs_ew_d; /* [63:0] */
int ew_ep_startspan;
int atomic;
int ew_cs_busy;
int ew_addr; /* [19:0] */ /* span address to mspan */
int ew_length; /* [11:0] */ /* spen length to mspan */
int spanbufrd; /* pop span from ew_ms span fifo */
/* O u t p u t S i g n a l s */
int ew_dxr; /* [22:0], s15.7 (single buffer) */
int ew_dxg; /* [22:0], s15.7 (single buffer) */
int ew_dxb; /* [22:0], s15.7 (single buffer) */
int ew_dxa; /* [22:0], s15.7 (single buffer) */
int ew_dxz; /* [22:0], s15.7 (single buffer) */
int ew_dxs; /* [22:0], s15.7 (single buffer) */
int ew_dxt; /* [22:0], s15.7 (single buffer) */
int ew_dxw; /* [22:0], s15.7 (single buffer) */
int ew_dyr; /* [22:0], s15.7 (single buffer) */
int ew_dyg; /* [22:0], s15.7 (single buffer) */
int ew_dyb; /* [22:0], s15.7 (single buffer) */
int ew_dya; /* [22:0], s15.7 (single buffer) */
int ew_dyz; /* [22:0], s15.7 (single buffer) */
int ew_dys; /* [22:0], s15.7 (single buffer) */
int ew_dyt; /* [22:0], s15.7 (single buffer) */
int ew_dyw; /* [22:0], s15.7 (single buffer) */
int st_dxr; /* [21:0], s10.11 (triple buffer) */
int st_dxg; /* [21:0], s10.11 (triple buffer) */
int st_dxb; /* [21:0], s10.11 (triple buffer) */
int st_dxa; /* [21:0], s10.11 (triple buffer) */
int st_dxz; /* [31:0], s15.16 (triple buffer) */
int st_dxs; /* [26:0], s10.16 (double buffer) */
int st_dxt; /* [26:0], s10.16 (double buffer) */
int st_dxw; /* [26:0], s.26 (double buffer) */
int st_dyr; /* [12:0], s10.2 (double buffer) */
int st_dyg; /* [12:0], s10.2 (double buffer) */
int st_dyb; /* [12:0], s10.2 (double buffer) */
int st_dya; /* [12:0], s10.2 (double buffer) */
int st_dyz; /* [21:0], (double buffer) */
/* New for LOD fix */
int st_dys; /* [16:0], (double buffer) */
int st_dyt; /* [16:0], (double buffer) */
int st_dyw; /* [16:0], (double buffer) */
int st_ncyc; /* number of cycles for s/t steppers, load overrides */
int64 color_image; /* [55:0], 3f 55:51, 43:32, 25:0 (unsynced) */
int64 z_image; /* [55:0], 3e 25:0 (unsynced) */
int64 tex_image; /* [55:0], 3d 55:51, 43:32, 25:0 (unsynced) */
int64 combine_mode; /* [55:0], 3c 55:0 (unsynced) */
int64 env_color; /* [55:0], 3b 31:0 (unsynced) */
int64 prim_color; /* [55:0], 3a 47:40, 39:0 (triple buffer) */
int64 blend_color; /* [55:0], 39 31:0 (unsynced) */
int64 fog_color; /* [55:0], 38 31:0 (unsynced) */
int64 fill_color; /* [55:0], 37 31:0 (unsynced) */
int64 other_modes; /* [55:0], 2f 53:0 (unsynced) */
int64 prim_depth; /* [31:0], 2e 31:16, 15:0 (triple buffer) */
int64 scissor; /* [55:0], 2d 55:32, 25:0 (single buffer) */
int64 convert; /* [55:0], 2c 53:0 (unsynced) */
int64 key_r; /* [55:0], 2b 27:0 (unsynced) */
int64 key_gb; /* [55:0], 2a 55:0 (unsynced) */
int rel_sync_tile; /* 28 (counter) */
int rel_sync_pipe; /* 27 (counter) */
int rel_sync_load; /* 31 (counter) */
int ew_image_load; /* tile(34),block(33),tlut(30) (pipe) */
int ew_scissor_load; /* tile(34),block(33),tlut(30) (pipe) */
int ew_stall_load; /* tile(34),block(33),tlut(30) (pipe) */
int ew_offset_load; /* tile(34),block(33),tlut(30) (pipe) */
int tc_load; /* tile(34),block(33),tlut(30) (pipe) */
int ew_major_sign;
int ew_offset_sign;
int shift_coord; /* load_block(33),tlut(34) (triple buffer) */
int level; /* [2:0], primitives (36,24,25,0f-08) (triple buffer) */
int tile; /* [2:0], primitives (36,24,25,0f-08) (triple buffer) */
int ew_major_left; /* primitives (36,24,25,0f-08) (pipe) */
int ew_minor_left; /* primitives (36,24,25,0f-08) (pipe) */
int ew_offset_left; /* primitives (36,24,25,0f-08) (pipe) */
int cv_left; /* primitives (36,24,25,0f-08) (pipe) */
int st_r_left; /* primitives (36,24,25,0f-08) (pipe) */
int st_g_left; /* primitives (36,24,25,0f-08) (pipe) */
int st_b_left; /* primitives (36,24,25,0f-08) (pipe) */
int st_a_left; /* primitives (36,24,25,0f-08) (pipe) */
int st_z_left; /* primitives (36,24,25,0f-08) (pipe) */
int st_s_left; /* primitives (36,24,25,0f-08) (pipe) */
int st_t_left; /* primitives (36,24,25,0f-08) (pipe) */
int st_w_left; /* primitives (36,24,25,0f-08) (pipe) */
int noise; /* random noise source, 9 bits */
int strobe_sync_full;
int spanbufmt;
int at_cs_busy; /* busy to force atomic primitives */
int ew_stall_tlut;
int ms_xi; /* [19:0] span initial address from fifo to mspan */
int ms_xf; /* [11:0] span final address from fifo to mspan */
int ms_count; /* [19:0] span final address from fifo to mspan */
int ms_load; /* is memspan doing a load ? */
int ms_load_tlut; /* loading tlut ? */
int ms_xdec; /* left or right triangle? (set==right) */
/* I n t e r n a l R e g i s t e r s */
int st_prim_dly[ST_SPAN_DLY]; /* delayed start primitive */
int st_dxr_dly[ST_DXR_INT_DLY]; /* [21:0], s10.11 */
int st_dxg_dly[ST_DXG_INT_DLY]; /* [21:0], s10.11 */
int st_dxb_dly[ST_DXB_INT_DLY]; /* [21:0], s10.11 */
int st_dxa_dly[ST_DXA_INT_DLY]; /* [21:0], s10.11 */
int st_dxz_dly[ST_DXZ_INT_DLY]; /* [31:0], s15.16 */
int st_dxs_dly[ST_DXS_INT_DLY]; /* [31:0], s15.16 */
int st_dxt_dly[ST_DXT_INT_DLY]; /* [31:0], s15.16 */
int st_dxw_dly[ST_DXW_INT_DLY]; /* [31:0], s15.16 */
int st_dyr_dly[ST_DYR_INT_DLY]; /* [12:0], s10.2 */
int st_dyg_dly[ST_DYG_INT_DLY]; /* [12:0], s10.2 */
int st_dyb_dly[ST_DYB_INT_DLY]; /* [12:0], s10.2 */
int st_dya_dly[ST_DYA_INT_DLY]; /* [12:0], s10.2 */
int st_dyz_dly[ST_DYZ_INT_DLY]; /* [21:0], */
/* New added for LOD fix */
int st_dys_dly[ST_DYS_INT_DLY]; /* [16:0], */
int st_dyt_dly[ST_DYT_INT_DLY]; /* [16:0], */
int st_dyw_dly[ST_DYW_INT_DLY]; /* [16:0], */
int rel_sync_pipe_dly[REL_SYNC_PIPE_DLY]; /* */
int rel_sync_full_dly[REL_SYNC_FULL_DLY]; /* */
int rel_sync_tile_dly[REL_SYNC_TILE_DLY]; /* */
int rel_sync_load_dly[REL_SYNC_LOAD_DLY]; /* */
int64 prim_color_dly[PRIM_COLOR_DLY]; /* */
int prim_depth_dly[PRIM_DEPTH_DLY]; /* */
int load_dly[LOAD_DLY]; /* */
int shift_coord_dly[SHIFT_COORD_DLY]; /* */
int level_dly[LEVEL_DLY]; /* */
int tile_dly[TILE_DLY]; /* */
int left_dly[LEFT_DLY]; /* */
int sign_dly[SIGN_DLY]; /* */
int ew_dxb_in; /* input latch, on start prim */
int ew_dxa_in;
int ew_dxs_in;
int ew_dxt_in;
unsigned int rand29b: 29;
unsigned int rand28b: 28;
unsigned int rand27b: 27;
unsigned int ew_ctrb; /* counter to guarantee atomic prim */
unsigned int reg_count; /* [11:0] */ /* delay span length */
unsigned int reg_xi; /* [19:0] */ /* delay span start address */
unsigned int span_wrp; /* [1:0] */ /* span fifo write pointer */
unsigned int span_sel; /* [1:0] */ /* span fifo read pointer */
int64 span_a; /* [55:0] */ /* span fifo node a */
int64 span_b; /* [55:0] */ /* span fifo node b */
int64 span_c; /* [55:0] */ /* span fifo node c */
int64 span_d; /* [55:0] */ /* span fifo node d */
int tlut_d1, tlut_d2, tlut_d3, tlut_d4; /* delay: set if cs_cmd==LOADTLUT*/
int tlut_d5, tlut_d6, tlut_d7, tlut_d8;
int tlut_d9, tlut_d10, tlut_d11, tlut_d12;
int tlut_d13;
int load_d1, load_d2, load_d3, load_d4; /* delay: set if load command */
int xdec_d1, xdec_d2, xdec_d3, xdec_d4; /* delay: set if right major */
} at_t;
/*
* Prototypes
*/
void at(at_t **pp0, at_t **pp1);
void at_init(at_t *p0, at_t *p1);
#endif /* ATTR_UNIT_INCLD */