#!smake
#
#  This makefile has rules for making both the executables
#  which make up the simulator, and for running test cases.
#
# $Revision: 1.1.1.1 $
#
COMMONPREF=cc
PRDEPTH = ../../..
include $(PRDEPTH)/PRdefs

#
#  Directories
#
SIMLIB		= ../../simlib
SRC    		= ../../src
HDR    		= ../../hdr
WIR    		= Wir
INDATA 		= InData
OUTDATA		= OutData
QSIM   		= ./qsim

SUBDIRS		= $(WIR)

#
#		Look in $(SRC) directory for C-sim source
#
.PATH:		$(SRC)

#
#  C Sources
#
TEST_FILES 	= \
        	$(SRC)/cc.c \
		expand.c \
        	driver.c \
        	cc_test_0.c

#
#  Object Files
#
TEST_OBJ 	= $(TEST_FILES:.c=.o)
TEST_OBJS    	= $(TEST_OBJ:T)

#
#  Header file Directories
#
LCINCS 		= -I. \
	 	-I$(SIMLIB) \
	 	-I$(HDR)

GCINCS 		=

#
# Compiler options
#
OPTIMIZER	= -g
LCOPTS		= -fullwarn

#
#  Linker Directories and Options
# 
LLDOPTS 	= -L. -L$(SIMLIB)
GLDOPTS 	=
LLDLIBS 	= -lsimlib

#
#  Verilog compiler options
#
LVCSOPTS = +incdir+$(PRDEPTH)/$(HW)/chip/rcp/inc

RTLOPTS	 = -y $(PRDEPTH)/$(HW)/chip/rcp/cc/src               	\
	   -y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell		\
	    +libext+.v+.vzd					\
	    -Mdir=rtlcsrc

SYNOPTS	 = -y $(PRDEPTH)/$(HW)/chip/rcp/cc/syn               	\
	   -y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell		\
	    +libext+.v+.vsyn					\
	    -Mdir=syncsrc

#DUMP	 = +dump

#
#  Default Targets
#
RTESTS 	= rtest000 rtest001 rtest002 rtest003 rtest004 rtest005 \
	  rtest006 rtest007 rtest008 rtest009 rtest010

STESTS 	= stest000 stest001 stest002 stest003 stest004 stest005 \
	  stest006 stest007 stest008 stest009 stest010

QTESTS 	= qtest000 qtest001 qtest002 qtest003 qtest004 qtest005 \
	  qtest006 qtest007 qtest008 qtest009 qtest010

LDIRT  	= rsimv rsimv.daidb driver.v csrc verilog.dump cc_test cc_test_0.c     \
	  $(INDATA)/inp??? $(INDATA)/inp???.tab				       \
	  $(OUTDATA)/test???.tab $(OUTDATA)/test???.mem $(OUTDATA)/test???.out \
	  fast???.out fast???.merge ${QSIM}/*.tab ${QSIM}/*.sim* ${QSIM}/*.trc*\
	  ${QSIM}/*.simlog*

#
#  SGI/Project Reality Common Rules
#
include $(PRDEPTH)/PRrules

#
#  Use HOST compile
#
.c.o:
	$(HOST_CC) $(CFLAGS) -c $*.c

$(COMMONTARGS): $(COMMONPREF)$$@
	$(SUBDIRS_MAKERULE)

default install rtests: $(_FORCE)
	@if test -n "$(USE_HW_ROOT)"; then \
		exec $(MAKE) HW=hw rtests_hw; \
	else \
		exec $(MAKE) HW=hw2 rtests_hw; \
	fi

stests: $(_FORCE)
	@if test -n "$(USE_HW_ROOT)"; then \
		exec $(MAKE) HW=hw stests_hw; \
	else \
		exec $(MAKE) HW=hw2 stests_hw; \
	fi

qtests: $(_FORCE)
	@if test -n "$(USE_HW_ROOT)"; then \
		exec $(MAKE) HW=hw qtests_hw; \
	else \
		exec $(MAKE) HW=hw2 qtests_hw; \
	fi


rtests_hw: $(RTESTS)

stests_hw: $(STESTS)

qtests_hw: $(_FORCE)
	(cd qsim; make)


#
#  Target for creating all .1 files, Viewlogic netlists
#
$(WIR)/cc_test.1: $(_FORCE)
	cd $(WIR); $(MAKE)

#
#  Compile 'C' processes
#
cc_test_0.c: $(WIR)/cc_test.1 cc_test.config $(XNET)
	$(XNET) -d $(WIR) cc_test -c cc_test.config

cc_test: cc_test_0.c $(SIMLIB) $(TEST_OBJS)
	$(HOST_CC) $(CFLAGS) $(TEST_OBJS) $(LDFLAGS) -o $@


#
# Compile Verilog processes
#

driver.v: $(OUTDATA)/test000.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 $(OUTDATA)/test000.tab > driver.v

rsimv: top_level.v driver.v $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) top_level.v driver.v -o $@

ssimv: top_level.vsyn driver.v $(_FORCE)
	$(VCS) $(VCSOPTS) $(SYNOPTS) top_level.vsyn driver.v -o $@

#
#  Test Targets
#

#
# test000  One cycle mode mux selects
#
rtest000: rsimv $(OUTDATA)/test000.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest000: ssimv $(OUTDATA)/test000.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast000: $(OUTDATA)/test000.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test000.tab $*.out > $*.merge

$(OUTDATA)/test000.tab: cc_test $(INDATA)/inp000.tab $(OUTDATA)/test000.tab.base
	./cc_test -i 0 -o all,test=000
	cmp -s $@ $@.base

#
# test001  Two cycle mode mux selects
#
rtest001: rsimv $(OUTDATA)/test001.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest001: ssimv $(OUTDATA)/test001.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast001: $(OUTDATA)/test001.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test001.tab $*.out > $*.merge

$(OUTDATA)/test001.tab: cc_test $(INDATA)/inp001.tab $(OUTDATA)/test001.tab.base
	./cc_test -i 1 -o all,test=001
	cmp -s $@ $@.base

#
# test002  Two cycle mode mux select tests with texel0 and combined inputs
#
rtest002: rsimv $(OUTDATA)/test002.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest002: ssimv $(OUTDATA)/test002.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast002: $(OUTDATA)/test002.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test002.tab $*.out > $*.merge

$(OUTDATA)/test002.tab: cc_test $(INDATA)/inp002.tab $(OUTDATA)/test002.tab.base
	./cc_test -i 2 -o all,test=002
	cmp -s $@ $@.base

#
# test003  Sanity test for start of span (st_span) signal
#
rtest003: rsimv $(OUTDATA)/test003.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest003: ssimv $(OUTDATA)/test003.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast003: $(OUTDATA)/test003.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test003.tab $*.out > $*.merge

$(OUTDATA)/test003.tab: cc_test $(INDATA)/inp003.tab $(OUTDATA)/test003.tab.base
	./cc_test -i 3 -o all,test=003
	cmp -s $@ $@.base

#
# test004  LERP tests
#
rtest004: rsimv $(OUTDATA)/test004.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest004: ssimv $(OUTDATA)/test004.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast004: $(OUTDATA)/test004.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test004.tab $*.out > $*.merge

$(OUTDATA)/test004.tab: cc_test $(INDATA)/inp004.tab $(OUTDATA)/test004.tab.base
	./cc_test -i 4 -o all,test=004
	cmp -s $@ $@.base

#
# test005  One cycle mode chroma keying test
#
rtest005: rsimv $(OUTDATA)/test005.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest005: ssimv $(OUTDATA)/test005.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast005: $(OUTDATA)/test005.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test005.tab $*.out > $*.merge

$(OUTDATA)/test005.tab: cc_test $(INDATA)/inp005.tab $(OUTDATA)/test005.tab.base
	./cc_test -i 5 -o all,test=005
	cmp -s $@ $@.base

#
# test006  Two cycle mode chroma keying test
#
rtest006: rsimv $(OUTDATA)/test006.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest006: ssimv $(OUTDATA)/test006.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast006: $(OUTDATA)/test006.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test006.tab $*.out > $*.merge

$(OUTDATA)/test006.tab: cc_test $(INDATA)/inp006.tab $(OUTDATA)/test006.tab.base
	./cc_test -i 6 -o all,test=006
	cmp -s $@ $@.base

#
# test007  Coverage test w/alpha_cov_select on
#
rtest007: rsimv $(OUTDATA)/test007.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest007: ssimv $(OUTDATA)/test007.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast007: $(OUTDATA)/test007.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test007.tab $*.out > $*.merge

$(OUTDATA)/test007.tab: cc_test $(INDATA)/inp007.tab $(OUTDATA)/test007.tab.base
	./cc_test -i 7 -o all,test=007
	cmp -s $@ $@.base

#
# test008  Coverage test w/alpha_cov_select offf
#
rtest008: rsimv $(OUTDATA)/test008.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest008: ssimv $(OUTDATA)/test008.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast008: $(OUTDATA)/test008.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test008.tab $*.out > $*.merge

$(OUTDATA)/test008.tab: cc_test $(INDATA)/inp008.tab $(OUTDATA)/test008.tab.base
	./cc_test -i 8 -o all,test=008
	cmp -s $@ $@.base

#
# test009  Texture edge test
#
rtest009: rsimv $(OUTDATA)/test009.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest009: ssimv $(OUTDATA)/test009.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast009: $(OUTDATA)/test009.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test009.tab $*.out > $*.merge

$(OUTDATA)/test009.tab: cc_test $(INDATA)/inp009.tab $(OUTDATA)/test009.tab.base
	./cc_test -i 9 -o all,test=009
	cmp -s $@ $@.base

#
# test010  dither_en sanity tests
#
rtest010: rsimv $(OUTDATA)/test010.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest010: ssimv $(OUTDATA)/test010.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast010: $(OUTDATA)/test010.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test010.tab $*.out > $*.merge

$(OUTDATA)/test010.tab: cc_test $(INDATA)/inp010.tab $(OUTDATA)/test010.tab.base
	./cc_test -i 10 -o all,test=010
	cmp -s $@ $@.base