inp001.v
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//
// inp001.v, example of verilog test vector generation program.
//
`timescale 100 ps / 100 ps
module inp000;
//
// Signals
//
reg gclk; // not printed
reg cycle;
reg [15:0] l;
reg [15:0] s;
reg [15:0] t;
reg [15:0] w;
reg [4:0] min_level;
reg detail_en;
reg sharp_en;
reg lod_en;
reg persp_en;
reg copy_7d;
reg copy_8d;
reg copy_9d;
reg samp_type;
reg tlut_en;
reg tlut_type;
reg [2:0] max_level;
reg [2:0] prim_tile;
reg load;
reg load_6d;
reg load_7d;
reg load_8d;
reg load_9d;
reg load_block;
reg dv;
reg exit1;
reg [9:0] x;
reg [9:0] y;
parameter Cycle = 160;
//
// Generate Clock
//
initial
begin
gclk = 1;
end
always
begin
#(Cycle/2) gclk = ~gclk;
end
//
// Generate test vectors
//
initial
begin
cycle = 0;
l[15:0] = 'h0;
s[15:0] = 'h0;
t[15:0] = 'h0;
w[15:0] = 'h0;
min_level[4:0] = 'h0;
detail_en = 0;
sharp_en = 0;
lod_en = 0;
persp_en = 0;
copy_7d = 0;
copy_8d = 0;
copy_9d = 0;
samp_type = 0;
tlut_en = 0;
tlut_type = 0;
max_level[2:0] = 'h0;
prim_tile[2:0] = 'h0;
load = 0;
load_6d = 0;
load_7d = 0;
load_8d = 0;
load_9d = 0;
load_block = 0;
dv = 0;
exit1 = 0;
x[9:0] = 'h0;
y[9:0] = 'h0;
#Cycle
#(Cycle * 3)
cycle = 1;
l[15:0] = 'haaa1;
s[15:0] = 'h0001;
t[15:0] = 'h0002;
lod_en = 1;
#(Cycle * 4)
$finish();
end
//
// Print Header
//
initial
begin
$write("#\n");
$write("# Created by inp001.v\n");
$write("#\n");
$write("gclk @C 0 8\n");
$write("cycle @I @E 0\n");
$write("l[15:0] \"%%04x\" @I\n");
$write("s[15:0] \"%%04x\" @I\n");
$write("t[15:0] \"%%04x\" @I\n");
$write("w[15:0] \"%%04x\" @I\n");
$write("min_level[4:0] \"%%02x\" @I\n");
$write("detail_en @I\n");
$write("sharp_en @I\n");
$write("lod_en @I\n");
$write("persp_en @I\n");
$write("copy_7d @I\n");
$write("copy_8d @I\n");
$write("copy_9d @I\n");
$write("samp_type @I\n");
$write("tlut_en @I\n");
$write("tlut_type @I\n");
$write("max_level[2:0] \"%%01x\" @I\n");
$write("prim_tile[2:0] \"%%01x\" @I\n");
$write("load @I\n");
$write("load_6d @I\n");
$write("load_7d @I\n");
$write("load_8d @I\n");
$write("load_9d @I\n");
$write("load_block @I\n");
$write("dv @I\n");
$write("exit1 @I\n");
$write("x[9:0] \"%%03x\" @I\n");
$write("y[9:0] \"%%03x\" @I\n");
$write("\n"); /* required blank line before vectors */
end
//
// Print Vectors
//
always @(posedge gclk)
begin
$write("%h ", cycle);
$write("0x%h ", l[15:0]);
$write("0x%h ", s[15:0]);
$write("0x%h ", t[15:0]);
$write("0x%h ", w[15:0]);
$write("0x%h ", min_level[4:0]);
$write("%h ", detail_en);
$write("%h ", sharp_en);
$write("%h ", lod_en);
$write("%h ", persp_en);
$write("%h ", copy_7d);
$write("%h ", copy_8d);
$write("%h ", copy_9d);
$write("%h ", samp_type);
$write("%h ", tlut_en);
$write("%h ", tlut_type);
$write("0x%h ", max_level[2:0]);
$write("0x%h ", prim_tile[2:0]);
$write("%h ", load);
$write("%h ", load_6d);
$write("%h ", load_7d);
$write("%h ", load_8d);
$write("%h ", load_9d);
$write("%h ", load_block);
$write("%h ", dv);
$write("%h ", exit1);
$write("0x%h ", x[9:0]);
$write("0x%h ", y[9:0]);
$write("\n");
end
endmodule