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#!smake -J 3

PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs

#
# Directories
#
HW = hw2
TCTM    = ../..
INDATA  = ../../InData

RTLOPTS = -y ../../fixture/src                                 \
          -y $(PRDEPTH)/$(HW)/chip/rcp/tc/src                     \
          -y $(PRDEPTH)/$(HW)/chip/rcp/tm/src                     \
          -y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell            \
          -y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram                \
           +libext+.v+.vzd                                     \
           +incdir+$(PRDEPTH)/$(HW)/chip/rcp/inc

SYNOPTS = -y ../../fixture/src                                 \
          -y $(PRDEPTH)/$(HW)/chip/rcp/tc/syn                     \
          -y $(PRDEPTH)/$(HW)/chip/rcp/tm/syn                     \
          -y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell            \
          -y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram                \
           +libext+.v+.vzd+.vsyn


LDIRT = driver*.v *.mem *.out vcs.log *.dump $(TMPDIR)/$(USER)_tex014 $(TMPDIR)/$(USER)_tex018 $(TMPDIR)/$(USER)_tex020 $(TMPDIR)/$(USER)_tex022 $(TMPDIR)/$(USER)_tex023 $(TMPDIR)/$(USER)_tex014_syn $(TMPDIR)/$(USER)_tex018_syn $(TMPDIR)/$(USER)_tex020_syn $(TMPDIR)/$(USER)_tex022_syn $(TMPDIR)/$(USER)_tex023_syn *.tab simv*

RTESTS = tex014 tex018 tex020 tex022 tex023
STESTS = tex014_syn tex018_syn tex020_syn tex022_syn tex023_syn
FAST  = fast014 fast018 fast020 fast022 fast023

ERROR = \
	@if  grep "ERROR IN SIMULATION" FILE ;	\
	then	echo "";    \
	else					\
		echo "NO ERRORS IN SIMULATION";	\
	fi 

default: $(RTESTS)

stests: $(STESTS)

include $(PRDEPTH)/PRrules

.mem.out: 

$(RTESTS): simv014 simv018 simv020 simv022 simv023

$(STESTS): simv014_syn simv018_syn simv020_syn simv022_syn simv023_syn

tex014.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp016.tab $(INDATA)/inp004.tab $@.base.Z
	(cd ../..; make test014)
	/usr/bsd/uncompress $@.base.Z
	cmp $@ $@.base
	/usr/bsd/compress $@.base

tex018.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp008.tab $@.base.Z
	(cd ../..; make test018)
	/usr/bsd/uncompress $@.base.Z
	cmp $@ $@.base
	/usr/bsd/compress $@.base

tex020.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp011.tab $(INDATA)/inp010.tab $@.base.Z
	(cd ../..; make test020)
	/usr/bsd/uncompress $@.base.Z
	cmp $@ $@.base
	/usr/bsd/compress $@.base

tex022.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp011.tab $(INDATA)/inp012.tab $@.base.Z
	(cd ../..; make test022)
	/usr/bsd/uncompress $@.base.Z
	cmp $@ $@.base
	/usr/bsd/compress $@.base

tex023.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp011.tab $(INDATA)/inp013.tab $@.base.Z
	(cd ../..; make test023)
	/usr/bsd/uncompress $@.base.Z
	cmp $@ $@.base
	/usr/bsd/compress $@.base

driver014.v: tex014.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 tex014.tab > driver014.v

driver018.v: tex018.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 tex018.tab > driver018.v

driver020.v: tex020.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 tex020.tab > driver020.v

driver022.v: tex022.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 tex022.tab > driver022.v

driver023.v: tex023.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 tex023.tab > driver023.v

simv014: top_level.v driver014.v tex014.mem $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv014 -Mdir="$(TMPDIR)/$(USER)_tex014" top_level.v driver014.v 
	@ if [ "$(DUMP)" ]; \
	then \
	(echo "simv014 +mem=tex014.mem > simv014.out"; simv014 -vcd verilog014.dump +mem=tex014.mem > simv014.out;) \
	else \
	(echo "simv014 +mem=tex014.mem > simv014.out"; simv014 +mem=tex014.mem +vcs+dumpvarsoff > simv014.out;) \
	fi 
	$(ERROR:FILE=simv014.out)
	$(LOG_ERROR)

simv018: top_level.v driver018.v tex018.mem $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv018 -Mdir="$(TMPDIR)/$(USER)_tex018" top_level.v driver018.v 
	@ if [ "$(DUMP)" ]; \
	then \
	(echo "simv018 +mem=tex018.mem > simv018.out"; simv018 -vcd verilog018.dump +mem=tex018.mem > simv018.out;) \
	else \
	(echo "simv018 +mem=tex018.mem > simv018.out"; simv018 +mem=tex018.mem +vcs+dumpvarsoff > simv018.out;) \
	fi 
	$(ERROR:FILE=simv018.out)
	$(LOG_ERROR)

simv020: top_level.v driver020.v tex020.mem $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv020 -Mdir="$(TMPDIR)/$(USER)_tex020" top_level.v driver020.v 
	@ if [ "$(DUMP)" ]; \
	then \
	(echo "simv020 +mem=tex020.mem > simv020.out"; simv020 -vcd verilog020.dump +mem=tex020.mem > simv020.out;) \
	else \
	(echo "simv020 +mem=tex020.mem > simv020.out"; simv020 +mem=tex020.mem +vcs+dumpvarsoff > simv020.out;) \
	fi 
	$(ERROR:FILE=simv020.out)
	$(LOG_ERROR)

simv022: top_level.v driver022.v tex022.mem $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv022 -Mdir="$(TMPDIR)/$(USER)_tex022" top_level.v driver022.v 
	@ if [ "$(DUMP)" ]; \
	then \
	(echo "simv022 +mem=tex022.mem > simv022.out"; simv022 -vcd verilog022.dump +mem=tex022.mem > simv022.out;) \
	else \
	(echo "simv022 +mem=tex022.mem > simv022.out"; simv022 +mem=tex022.mem +vcs+dumpvarsoff > simv022.out;) \
	fi 
	$(ERROR:FILE=simv022.out)
	$(LOG_ERROR)

simv023: top_level.v driver023.v tex023.mem $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv023 -Mdir="$(TMPDIR)/$(USER)_tex023" top_level.v driver023.v 
	@ if [ "$(DUMP)" ]; \
	then \
	(echo "simv023 +mem=tex023.mem > simv023.out"; simv023 -vcd verilog023.dump +mem=tex023.mem > simv023.out;) \
	else \
	(echo "simv023 +mem=tex023.mem > simv023.out"; simv023 +mem=tex023.mem +vcs+dumpvarsoff > simv023.out;) \
	fi 
	$(ERROR:FILE=simv023.out)
	$(LOG_ERROR)

simv014_syn: top_level.vsyn driver014.v tex014.mem $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so $(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
	-Mdir="$(TMPDIR)/$(USER)_tex014_syn" top_level.vsyn driver014.v 
	@ if [ "$(DUMP)" ]; \
        then \
	(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex014.mem > $@.out"; $@ -vcd verilog014_syn.dump +mem=tex014.mem > $@.out;) \
        else \
        (LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex014.mem > $@.out"; $@ +mem=tex014.mem +vcs+dumpvarsoff > $@.out;) \
        fi 
	$(ERROR:FILE=simv014_syn.out)
	$(LOG_ERROR)

simv018_syn: top_level.vsyn driver018.v tex018.mem $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so $(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
	-Mdir="$(TMPDIR)/$(USER)_tex018_syn" top_level.vsyn driver018.v 
	@ if [ "$(DUMP)" ]; \
        then \
	(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex018.mem > $@.out"; $@ -vcd verilog018_syn.dump +mem=tex018.mem > $@.out;) \
        else \
        (LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex018.mem > $@.out"; $@ +mem=tex018.mem +vcs+dumpvarsoff > $@.out;) \
        fi 
	$(ERROR:FILE=simv018_syn.out)
	$(LOG_ERROR)

simv020_syn: top_level.vsyn driver020.v tex020.mem $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so $(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
	-Mdir="$(TMPDIR)/$(USER)_tex020_syn" top_level.vsyn driver020.v 
	@ if [ "$(DUMP)" ]; \
        then \
	(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex020.mem > $@.out"; $@ -vcd verilog020_syn.dump +mem=tex020.mem > $@.out;) \
        else \
        (LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex020.mem > $@.out"; $@ +mem=tex020.mem +vcs+dumpvarsoff > $@.out;) \
        fi 
	$(ERROR:FILE=simv020_syn.out)
	$(LOG_ERROR)

simv022_syn: top_level.vsyn driver022.v tex022.mem $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so $(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
	-Mdir="$(TMPDIR)/$(USER)_tex022_syn" top_level.vsyn driver022.v 
	@ if [ "$(DUMP)" ]; \
        then \
	(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex022.mem > $@.out"; $@ -vcd verilog022_syn.dump +mem=tex022.mem > $@.out;) \
        else \
        (LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex022.mem > $@.out"; $@ +mem=tex022.mem +vcs+dumpvarsoff > $@.out;) \
        fi 
	$(ERROR:FILE=simv022_syn.out)
	$(LOG_ERROR)

simv023_syn: top_level.vsyn driver023.v tex023.mem $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so $(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
	-Mdir="$(TMPDIR)/$(USER)_tex023_syn" top_level.vsyn driver023.v 
	@ if [ "$(DUMP)" ]; \
        then \
	(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex023.mem > $@.out"; $@ -vcd verilog023_syn.dump +mem=tex023.mem > $@.out;) \
        else \
        (LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tex023.mem > $@.out"; $@ +mem=tex023.mem +vcs+dumpvarsoff > $@.out;) \
        fi 
	$(ERROR:FILE=simv023_syn.out)
	$(LOG_ERROR)

fast: $(FAST)	

fast014: tex014.mem
	simv014 +mem=$? | tee $*.out

fast018: tex018.mem
	simv018 +mem=$? | tee $*.out

fast020: tex020.mem
	simv020 +mem=$? | tee $*.out

fast022: tex022.mem
	simv022 +mem=$? | tee $*.out

fast023: tex023.mem
	simv023 +mem=$? | tee $*.out