test.6
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####################################################
# this file produced by tab2sim #
# #
# tab2sim written by Rob Moore #
# Silicon Graphics, Inc. #
# November 1994 #
####################################################
alias i inputs
alias c charged
alias t test
forced high vdd
forced low vss
echo #
echo # Test multiple clocks
echo #
clock gclk 0(8.00) 1(8.00)
clock fclk 0(16.00) 1(16.00)
clock eclk 0(32.00) 1(32.00)
echo #a b c d e f g h i
echo #original sim at cycle :0 absolute time:0.00
l sig_h
s 1.00
h sig_f
s 1.00
i 'h0 sig_a
s 1.00
i 'h00 sig_e
s 12.00
t sig_b 'h0
s 2.00
i 'h0 sig_i
s 1.00
i 'h1 sig_a
s 13.00
t sig_b 'h1
s 3.00
i 'h2 sig_a
s 1.00
i 'h11 sig_e
s 12.00
t sig_b 'h0
s 3.00
i 'h3 sig_a
s 12.00
t sig_c 'haaa
s 1.00
t sig_b 'h1
s 3.00
i 'h4 sig_a
s 13.00
t sig_b 'h1
s 16.00
t sig_b 'h1
s 2.00
h sig_f
s 2.00
i 'h33 sig_e
s 12.00
t sig_b 'h0
s 3.00
i 'h7 sig_a
s 12.00
t sig_c 'h444
s 1.00
t sig_b 'h0
echo #a b c d e f g h i
s 3.00
i 'h8 sig_a
s 1.00
i 'h44 sig_e
s 12.00
t sig_b 'h1
s 2.00
i 'h1 sig_i
s 14.00
t sig_b 'h1
s 3.00
i 'ha sig_a
s 1.00
i 'h55 sig_e
s 12.00
t sig_b 'h1
s 3.00
i 'hb sig_a
s 12.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 3.00
i 'hc sig_a
s 1.00
i 'h66 sig_e
s 12.00
t sig_b 'h0
s 3.00
i 'hd sig_a
s 13.00
t sig_b 'h1
s 3.00
i 'he sig_a
s 1.00
i 'h77 sig_e
s 12.00
t sig_b 'h1
s 3.00
i 'hf sig_a
s 12.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
echo #a b c d e f g h i
s 1.00
h sig_h
s 3.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 2.00
i 'h3 sig_i
s 13.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 4.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
echo #a b c d e f g h i
s 1.00
echo #original sim at cycle :20 absolute time:320.00
l sig_h
s 3.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 2.00
i 'h4 sig_i
s 13.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 4.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 1.00
z sig_h
s 3.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 2.00
i 'h5 sig_i
s 13.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 4.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
echo #a b c d e f g h i
s 1.00
h sig_h
s 3.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 2.00
c * sig_i
s 13.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 4.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 4.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 4.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
echo #a b c d e f g h i
s 1.00
l sig_h
s 3.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 2.00
i 'h4 sig_i
s 13.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 4.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 1.00
echo #original sim at cycle :40 absolute time:640.00
s 3.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
s 4.00
i 'h77 sig_e
s 12.00
t sig_b 'h0
s 15.00
t sig_c 'haaa
s 1.00
t sig_b 'h0
echo #a b c d e f g h i
s 0.00