#!/usr/local/bin/perl

if ($ENV{"ROOT"}) {
   $ROOT = $ENV{"ROOT"};
  }
else {
  die "ROOT env not set. Plaase set ROOT environment first \n";
  }


$RNSRC =  $ROOT."/PR/rspsim/random";
$RNSRC_NAME =  $ROOT."/PR/rspsim/random";
$VUREGRES =  $ROOT."/PR/rspsim/vuregre";

$TOOL =   $VUREGRES."/bin";
$RSPASM = $ROOT."/PR/rspasm";
$RSPSIM = $ROOT."/PR/rspsim";
$VCSDIR = "/ecad/vcs/vcs_2.2/sgi";


$WORKDIR = `pwd`;
chop($WORKDIR);
$TESTDIR = $WORKDIR."/rtests";
$TESTDIR_NAME = $WORKDIR."/rtests";
$TESTDIR_CT = $TESTDIR."/ctrace";
$DESIGNC = $WORKDIR."/designc"; 


$OPTION_VCSCOMPILE = 1;
$OPTION_VCSRUN = 1;
$OPTION_DUMPVARS = 0;
$OPTION_CTRACE = 0;
$OPTION_ASM = 1;
@PlusArgs = ();
$ALL_DIAGS = 1;

while ($#ARGV >= 0) {

    if ($ARGV[0] eq '-nocompile') {
      shift (@ARGV);
      $OPTION_VCSCOMPILE = 0;
      $OPTION_ASM = 0;
    }
    elsif ($ARGV[0] eq '-local') {
      shift (@ARGV);
      $TESTDIR_NAME = "./rtests";
      $RNSRC_NAME = "../..";
    }
    elsif ($ARGV[0] eq '-noasm') {
      shift (@ARGV);
      $OPTION_ASM = 0;
    }
    elsif ($ARGV[0] eq '-norun') {
      shift (@ARGV);
      $OPTION_VCSRUN = 0;
    }
    elsif ($ARGV[0] eq '+dumpvars') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
      $OPTION_DUMPVARS = 1;
    }
    elsif ($ARGV[0] eq '+ctrace') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
      $OPTION_CTRACE = 1;
    }
    elsif ($ARGV[0] eq '+random_halt') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+random_ddma') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+random_idma') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+eod_rst') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
      $OPTION_CTRACE = 1;
    }
    elsif ($ARGV[0] =~ /^\+diag=/) {
      ($TEMP,$DIAG) = split(/=/,shift(@ARGV));
      $PlusArgs = push(@PlusArgs,"+diag_".$DIAG);
      $ALL_DIAGS = 0;
    }
    elsif ($ARGV[0] =~ /^\+seed=/) {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '-h') {
      shift (@ARGV);
      print "\n";
      print "\n";
      print "Usage: rsp_regression [options]\n";
      print "\n";
      print "\n";
      print "  options:\n";
      print "  -h           //Help \n";
      print "\n";
      print "  -nocompile   //This skips VCS compile of your design. Useful if you want to only \n";
      print "                 re-run the previously compiled design \n";
      print "\n";
      print "  -norun       //This does not execute simulation. Only compiles. \n";
      print "\n";
      print "\n";
      print "  +dumpvars     //This causes the \$dumpvars to take effect. default is no dump. \n";
      print "                  CAUTION: verilog.dump can be very large file for big simulation. \n";
      print "\n";
      print "  +ctrace       //This enables the regi/mem traces to compare with verilog\n";
      print "\n";
      print "  +eod_rst       //Resets rsp after end of each diag\n";
      print "\n";
      print "  +diag=<diag_name>  //This passes the diag_name as +arg to simulation and \n";
      print "                       simulate only with given diag. You can provide more then \n";
      print "                       one diag name as shown below. \n";
      print "                        +diag=<diag_1> +diag=<diag_2> .... +diag=<diag_3> \n";
      print "\n";
      print "                       If this option is not given, then default is all the \n";
      print "                       diags specified in testssuite. \n";
      print "\n";
      print "                       With this feature, you can compile once with all the \n";
      print "                       diags in testsuite and choose to only run the ones you want. \n";
      print "\n";
      exit; 
    }
    else {
    die "Illigal option provided \n";
    }

} #while ($#ARGV >= 0)

if ($ALL_DIAGS==1) {
    $PlusArgs = push(@PlusArgs,"+AllDiags");
    }

if (!(-e $TESTDIR && -d $TESTDIR)) {
  print "Creating the $TESTDIR directory\n";
  mkdir ($TESTDIR,0777)    || die "Cant make $TESTDIR \n";
  }
if (!(-e $TESTDIR_CT && -d $TESTDIR_CT)) {
  print "Creating the $TESTDIR_CT directory\n";
  mkdir ($TESTDIR_CT,0777)    || die "Cant make $TESTDIR_CT \n";
  }

if (!(-e $DESIGNC && -d $DESIGNC)) {
  print "Creating the $DESIGNC directory\n";
  mkdir ($DESIGNC,0777) || die "Cant make $DESIGNC \n";
  } 

if ( -r $VUREGRES."/regression/vcs_makefile") {
    system("cp $VUREGRES/regression/vcs_makefile $DESIGNC/Makefile")==0 
       || die " System Call interrupt";
    chmod(0666,$DESIGNC."/Makefile");
}
else {
  die "can not get vcs_makefile. Please p_tupdate $VUREGRES \n";
}

if (!(-r $VUREGRES."/regression/rsp_regr_include.v")){
  die "rsp_regr_include.v not found. Please p_tupdate $VUREGRES \n";
  }

if ( -r $VUREGRES."/regression/rsp_regression.makefile") {
    system("cp $VUREGRES/regression/rsp_regression.makefile Makefile")==0
       || die " System Call interrupt";
    chmod(0666,Makefile);
}
else {
  die "can not get rsp_regression.makefile. Please p_tupdate $VUREGRES \n";
}

if ($OPTION_ASM) {

   if (!(-r "random_testsuite")){
      print "Getting file $RNSRC/random_testsuite \n";
      system("cp $RNSRC/random_testsuite $WORKDIR")==0
       || die " System Call interrupt";
      chmod(0666,$WORKDIR."/random_testsuite");
    }

  open(TESTSUITE,"random_testsuite") || die "Cant open random_testsuite \n";
  open(TESTSKIPPED,">tests.skipped") || die "Cant open tests.skipped \n";

  $test_num=0;

  while ($_= <TESTSUITE>) {

     split;

     $RNTEST = 0;

     $TEST_TOKEN = $_[0]; #test
     $TEST       = $_[1]; #test
     $FILE_TYPE  = "out";

     if ($TEST_TOKEN eq "tst") {

        $TESTNAME_FULL = $RNSRC_NAME."/".$TEST;
        open(MAKEFILE,">$TESTDIR/Makefile") || die "Cant open $TESTDIR/Makefile \n";

	print "test is $TEST \n";
	
        chdir ($TESTDIR) || die "Cant go to $TESTDIR \n";
        print MAKEFILE "\n";
	print MAKEFILE "SRC = $TEST.dat $TEST.out $TEST.regs ctrace/$TEST.ctrace $TEST.lst $TEST.vreg\n";
	print MAKEFILE "TARGET = $TEST.IMEM \n";
	print MAKEFILE "TOOL = $TOOL/out2IMEM $TOOL/dat2DMEM $TOOL/trace2ver $TOOL/reg2IREG $TOOL/reg2VREG \n";
	print MAKEFILE "\n";
	print MAKEFILE "\$(TARGET): \$(SRC) \$(TOOL) \n";
        print MAKEFILE "\tod -vX $TEST.dat  | $TOOL/dat2DMEM > $TEST.DMEM\n";
        print MAKEFILE "\tod -vX $TEST.regs | $TOOL/reg2IREG > $TEST.IREG\n";
        print MAKEFILE "\tod -vX $TEST.vreg | $TOOL/reg2VREG > $TEST.VREG\n";
        print MAKEFILE "\t(cd ctrace; $TOOL/trace2ver $TEST random)\n";
        print MAKEFILE "\tod -vX $TEST.out  | $TOOL/out2IMEM > $TEST.IMEM\n";
	print MAKEFILE "\n";

	print MAKEFILE "\n";
	print MAKEFILE "$TEST.dat: $TESTNAME_FULL.dat\n";
	print MAKEFILE "\tcp $TESTNAME_FULL.dat $TEST.dat\n";
	print MAKEFILE "\tchmod +w $TEST.dat\n";

	print MAKEFILE "\n";
	print MAKEFILE "$TEST.lst: $TESTNAME_FULL.lst\n";
	print MAKEFILE "\tcp $TESTNAME_FULL.lst $TEST.lst\n";
	print MAKEFILE "\tchmod +w $TEST.lst\n";

	print MAKEFILE "\n";
	print MAKEFILE "$TEST.out: $TESTNAME_FULL.out\n";
	print MAKEFILE "\tcp $TESTNAME_FULL.out $TEST.out\n";
	print MAKEFILE "\tchmod +w $TEST.out\n";

	print MAKEFILE "\n";
	print MAKEFILE "$TEST.vreg: $TESTNAME_FULL.vreg\n";
	print MAKEFILE "\tcp $TESTNAME_FULL.vreg $TEST.vreg\n";
	print MAKEFILE "\tchmod +w $TEST.vreg\n";

	print MAKEFILE "\n";
	print MAKEFILE "$TEST.regs: $TESTNAME_FULL.regs\n";
	print MAKEFILE "\tcp $TESTNAME_FULL.regs $TEST.regs\n";
	print MAKEFILE "\tchmod +w $TEST.regs\n";

	print MAKEFILE "\n";
	print MAKEFILE "ctrace/$TEST.ctrace: $TESTNAME_FULL.ctrace\n";
	print MAKEFILE "\tcp $TESTNAME_FULL.ctrace ctrace/$TEST.ctrace\n";
	print MAKEFILE "\tchmod +w ctrace/$TEST.ctrace\n";
	print MAKEFILE "\n";

	close(MAKEFILE);
		
        if (system("make")==0) {
	    $ARRY[$test_num] = $TEST;
	    $test_num++;
	  }
        else {
	       print "\n\n****ERROR:asm steps: test skipped\n\n";
	       print TESTSKIPPED "$_ skipped due to Error\n";
   	       system("touch $TESTDIR/$TEST.IMEM")==0 || die "System Interrupt";
   	       system("rm $TESTDIR/$TEST.IMEM")==0 || die "System Interrupt";
          }

	chdir ($WORKDIR) || die "Cant go to parent \n";


      }
  } #while

close(TESTSKIPPED);
if (-z $WORKDIR."/tests.skipped") {
   system("rm $WORKDIR/tests.skipped")==0 || die "System Interrupt";
   }    

  if ($test_num==0) {
   die "NO TESTS found in testsuite \n";
   }
  open(OUT,">rsp_tests.v") || die "Cant open rsp_tests.v";
  
  $TEMP = $VUREGRES."/regression/rsp_regr_include.v";
  
  print OUT "\n";
  print OUT "`timescale 1ns / 10ps \n";
  print OUT "\n";
  print OUT "module rsp_tests;\n";
  print OUT "\n";
  print OUT "\n";
  print OUT "`include  \"$TEMP\""; 
  print OUT "\n";
  print OUT "\n";

  for ($i=0; $i<$test_num; $i++) {
     $TEST      = $ARRY[$i];
     print OUT "reg diag_$TEST;\n";
    }
  print OUT "initial\n";
  print OUT "    begin\n";
  for ($i=0; $i<$test_num; $i++) {
     $TEST      = $ARRY[$i];
     print OUT "       diag_$TEST=0;\n";
     print OUT "       if (\$test\$plusargs(\"diag_$TEST\"))\n";
     print OUT "           diag_$TEST=1;\n";
     print OUT "\n";
   }
  print OUT "    end\n";
  print OUT "\n";

  print OUT "initial \n";
  print OUT "begin \n";
  print OUT "@(posedge `CLK);";
  print OUT "\n";
  print OUT "\n";
  print OUT "\$fwrite(fp,\"\\n\\n\");\n";
  print OUT "\n";
  print OUT "\n";
  print OUT "wait (`Reset_l==1'b1);\n";
  print OUT "repeat (4) @(posedge `CLK); \n";
  print OUT "\n";
  
  for ($i=0; $i<$test_num; $i++) {
     $TEST      = $ARRY[$i];
     $test_code = "2'b10";

     $j = $i+1;
     print OUT "\n";
     print OUT "/*********************************************\n";
     print OUT " * (Test# $j)  Test Name: $TEST \n";
     print OUT " *********************************************/\n";
     print OUT "\n";
     print OUT "if (diag_$TEST || AllDiags) \n";
     print OUT "begin \n";
     print OUT "   \$display(\$time,\" TEST $TEST starts\"); \n";
     print OUT "   \$readmemh(\"$TESTDIR_NAME/$TEST.IMEM\",`IMEM); \n";
     print OUT "   \$readmemh(\"$TESTDIR_NAME/$TEST.DMEM\",mem); \n";
     print OUT "   \$readmemh(\"$TESTDIR_NAME/$TEST.IREG\",ireg_mem); \n";
     print OUT "   \$readmemh(\"$TESTDIR_NAME/$TEST.VREG\",vreg_mem); \n";
     print OUT "   if (ctrace) \n";
     print OUT "   begin \n";
     print OUT "     \$readmemh(\"$TESTDIR_NAME/ctrace/$TEST.trSU\",`tr.su_mem); \n";
     print OUT "     \$readmemh(\"$TESTDIR_NAME/ctrace/$TEST.trVU\",`tr.vu_mem); \n";
     print OUT "     \$readmemh(\"$TESTDIR_NAME/ctrace/$TEST.trDM\",`tr.dm_mem); \n";
     print OUT "     \$readmemh(\"$TESTDIR_NAME/ctrace/$TEST.NC\",  `tr.nc_mem); \n";
     print OUT "   end \n";
     print OUT "   rundiag($test_code,\"$TEST\");\n";
     print OUT "   \$display(\$time,\"TEST $TEST ends\"); \n";
     print OUT "end\n";
  }
  print OUT "\n";
  print OUT "\n";
  print OUT "\$finish; \n";
  print OUT "\n";
  print OUT "end \n";
  print OUT "\n";
  print OUT "endmodule \n";
  
  close(TESTSUITE);
  close(OUT);

}

if ($OPTION_VCSCOMPILE) {
  print "\n\nVCS Compile in progress\n\n";

  chdir ("$WORKDIR");
    if (-r "designc/simv"){
        system("rm designc/simv")==0 || die "System Interrupt";
        }
    system("make simv")==0 || die "VCS compile system call interupt";
}

if ($OPTION_VCSRUN) {
  chdir ("$WORKDIR");
  print "\n\n Running Simulation in BATCH mode \n\n";
  print "plusargs passed to vcs are: @PlusArgs \n";

  system("/bin/csh -c 'setenv LD_LIBRARY_PATH $VCSDIR/lib; ".
         "time  designc/simv -q @PlusArgs' > random.stdout")==0
               || die("Interrupt occured, cannot run regression");

  print "SImulation Complete\n";
  system("mv regression.log random.log")==0 || die("Interrupt occured");
}