make_reality_makefile2
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#!/usr/sbin/perl
#
#
$printoff = 0;
$LARGE_TRACE_BUFFER = 0;
$LARGE_TIMEOUT = 0;
$MISC_TESTS = 0;
$RSP_GATE = 0;
while ($#ARGV >= 0) {
if ($ARGV[0] eq '-LARGE_TRACE_BUFFER') {
shift (@ARGV);
$LARGE_TRACE_BUFFER = 1;
}
elsif ($ARGV[0] eq '-LARGE_TIMEOUT') {
shift (@ARGV);
$LARGE_TIMEOUT = 1;
}
elsif ($ARGV[0] eq '-MISC_TESTS') {
shift (@ARGV);
$MISC_TESTS = 1;
}
else {
die "Illigal option provided \n";
}
} #while ($#ARGV >= 0)
while (<>) {
split;
if ($_[0] eq "PRDEPTH") {
print "PRDEPTH = \$(ROOT)/PR\n";
print "REALITY_SIM = \$(PRDEPTH)/hw2/chip/sim\n";
print "REGRESSION = \$(PRDEPTH)/rspsim/vuregre/regression2\n";
}
elsif ($_[0] eq "LVCSOPTS") {
print "VSYNPATH = \$(PRDEPTH)/PR/hw2/chip/rcp/rsp/vsyn\n";
print "RSP_GATE_FILES = \\\n";
print " \$(VSYNPATH)/divctl.vsyn \\\n";
print " \$(VSYNPATH)/io_cmd_dma.vsyn \\\n";
print " \$(VSYNPATH)/io_mem_dma.vsyn \\\n";
print " \$(VSYNPATH)/ls.vsyn \\\n";
print " \$(VSYNPATH)/rspbusses.vsyn \\\n";
print " \$(VSYNPATH)/su.vsyn \\\n";
print " \$(VSYNPATH)/vu.vsyn \\\n";
print " \$(VSYNPATH)/vusl.vsyn \\\n";
print "\n";
print "\n";
print "RSPOPTS = \\\n";
print " -P \$(PRDEPTH)/lib/librcppli/rcppli.tab \$(PRDEPTH)/lib/librcppli/librcppli.a \\\n";
print " -y \$(PRDEPTH)/hw2/chip/sim \\\n";
print " +incdir+\$(PRDEPTH)/hw2/chip/sim \\\n";
print " +incdir+\$(REGRESSION) \\\n";
print " +define+REALITY_RSP_REGRESSION \\\n";
print " +define+RSP_MON \\\n";
if ($LARGE_TRACE_BUFFER) {
print " +define+LARGE_TRACE_BUFFER \\\n";
}
if ($LARGE_TIMEOUT) {
print " +define+LARGE_TIMEOUT \\\n";
}
print "\n";
print "\n";
print "$_";
}
elsif ($_[0] eq "GATE_RCP") {
print "GATE_RCP = \$(REALITY_SIM)/rcp.vsyn \n";
}
elsif ($_[0] eq "simv:") {
##################################################
print "simv_rcp_misc_test: \$(REALITY_SIM)/reality.v rcp_misc_test.v \$(_FORCE) \n";
print " \$(VCS) \$(VCSOPTS) \$(RSPOPTS) -Mdir=designc -o \$@ \$(REALITY_SIM)/reality.v \\\n";
print " rcp_misc_test.v \\\n";
print "\n\n";
##################################################
print "simv_rcpgate_misc_test: \$(REALITY_SIM)/reality.v rcp_misc_test.v \$(_FORCE) \n";
print " \$(VCS) \$(GATE_LVCSOPTS) \$(RSPOPTS) \$(GVCSOPTS) -Mdir=designc \\\n";
print " -o \$@ \$(REALITY_SIM)/reality.v rcp_misc_test.v \\\n";
print " \$(GATE_FILES) +define+RSP_GATE +define+GATE_LEVEL \\\n";
print "\n\n";
##################################################
print "simv_rsp_regr: \$(REALITY_SIM)/reality.v \$(REGRESSION)/rsp_ctrace.v \$(_FORCE) \n";
print " \$(VCS) \$(VCSOPTS) \$(RSPOPTS) -Mdir=designc -o \$@ \$(REALITY_SIM)/reality.v \\\n";
#print " \$(REALITY_SIM)/dummy_rdp.v \$(REGRESSION)/rsp_ctrace.v \\\n";
print " \$(REGRESSION)/rsp_ctrace.v \\\n";
if ($MISC_TESTS==1) {
print " misc_tests.v \\\n";
}
else {
print " rsp_tests.v \\\n";
}
print "\n\n";
##################################################
print "simv_rsp_regr_gate: \$(REALITY_SIM)/reality.v \$(REGRESSION)/rsp_ctrace.v \$(_FORCE) \n";
print " \$(VCS) \$(VCSOPTS) \$(RSPOPTS) -Mdir=designc -o \$@ \$(REALITY_SIM)/reality.v \\\n";
print " \$(REALITY_SIM)/dummy_rdp.v \$(REGRESSION)/rsp_ctrace.v \\\n";
print " \$(RSP_GATE_FILES) +define+RSP_GATE \\\n";
if ($MISC_TESTS==1) {
print " misc_tests.v \\\n";
}
else {
print " rsp_tests.v \\\n";
}
print "\n\n";
##################################################
print "rcpgate_rsp_simv: \$(REALITY_SIM)/reality.v \$(REGRESSION)/rcpgate_rsp_ctrace.v \$(_FORCE) \n";
print " VCS_RUNTIME=\$(VCSDIR)/lib/libvcs.a \\\n";
print " \$(VCS) \$(GATE_LVCSOPTS) \$(RSPOPTS) \$(GVCSOPTS) -Mdir=designc \\\n";
print " -o \$@ \$(REALITY_SIM)/reality.v \$(REGRESSION)/rcpgate_rsp_ctrace.v \\\n";
print " \$(GATE_FILES) +define+RSP_GATE +define+GATE_LEVEL \\\n";
if ($MISC_TESTS==1) {
print " misc_tests.v \\\n";
}
else {
print " rsp_tests.v \\\n";
}
print "\n\n";
##################################################
print "$_";
}
else {
print "$_";
}
}