/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */


	/*
	 *  ms_ldst  -  Process loads and stores for the MXS simulator
	 *
	 *	Jim Bennett
	 *	1993, 1994, 1995
	 */

#include <sys/types.h>
#include <string.h>
#include <stdlib.h>
#include "ms.h"
#include "common_cache.h"
#include "simutil.h"
#include "memsys.h"

#ifdef MIPSY_MXS
#include "hw_events.h"
#include "cpu_state.h"
#include "memref.h"
#endif

/* These are needed to make the DCACHE_TAG and DCACHE_INDEXOF macros work */
#define dIndexMask  (DCACHE_INDEX - 1)
#define dTagShift   (log2DCACHE_SIZE - 1)

static int ms_lsop (struct s_cpu_state *st, struct s_lsq *ls,
			struct s_ldst_buffer *ldst_ent, int update_inst);
static int ms_lsop_uncached (struct s_cpu_state *st, struct s_lsq *ls);
static int ms_cache (struct s_cpu_state *st, struct s_lsq *ls,
					struct s_ldst_buffer *entry);

static	int	ldst_buffer_conflict (struct s_cpu_state *st,
					struct s_ldst_buffer *ldst_ent);
static struct s_ldst_buffer *
	ldst_buffer_alloc (struct s_cpu_state *st, int paddr, int lstype);
static	void	ldst_buffer_free (struct s_cpu_state *st,
					struct s_ldst_buffer *entry);
static	void	ldst_buffer_write(struct s_cpu_state *st,
		  struct s_ldst_buffer *entry, int paddr, char *data,int size);
static	int	ldst_buffer_updateRead (struct s_cpu_state *st,
		  struct s_ldst_buffer *entry, int paddr, char *data,int size);

static	int	recurse_unstall (struct s_cpu_state *st, int br_node);
static	void	set_new_excuse (struct s_cpu_state *st, int reg, int excuse);

#ifdef MIPSY_MXS

#define	WouldFault(st, lstype, addr) (0)

#else

#define	WouldFault(st, lstype, addr)					\
	(is_misaligned (lstype, addr) ||				\
    (!((((addr) >= pmap.text_base) && ((addr) < pmap.max_text)) ||	\
       (((addr) >= pmap.data_base) && ((addr) < pmap.data_top)) )))

#endif

/*
 * ldst_init - Initialize the load/store unit data structures. This
 *	     routine should be called after each exception.
 */
void ldst_init( struct s_cpu_state *st)
	{
	int i;

	for (i = 0; i < LDST_BUFFER_SIZE; i++)
		{
		st->ldst_buffer[i].next = &st->ldst_buffer[i+1];
		st->ldst_buffer[i].prev = &st->ldst_buffer[i-1];
		st->ldst_buffer[i].missTag = (void *) -1;
		st->ldst_buffer[i].ls = &st->lsq[i];
		st->lsq[i].ldst_ent = &st->ldst_buffer[i];
		}
	st->ldst_buffer[0].prev = NULL;
	st->ldst_buffer[LDST_BUFFER_SIZE-1].next = NULL;

		/* All entries go on the free list to start	*/
	st->ldst_head = NULL;
	st->ldst_tail = NULL;
	st->ldst_nextReserved = NULL;
	st->ldst_nextAvail = &st->ldst_buffer[0];
	}


	/*
	 *  ms_ldst_dep  -  Update load/store dependencies
	 */

void ms_ldst_dep (struct s_cpu_state *st)
	{

#ifdef ONE_PHASE_LS
		/* For a one phase load/store, update the IWIN_LDST_DEP	*/
		/* flag of instructions at the head of the chain.	*/
	int	inum;

	inum = st->iwin_head_ldst;
	if (inum >= 0)
		{
			/* Disallow speculative stores.		*/
		if ((st->iwin_flags [inum] & (IWIN_STORE | IWIN_SPEC)) ==
						(IWIN_STORE | IWIN_SPEC))
			return;

		st->iwin_flags [inum] &= ~IWIN_LDST_DEP;
		CheckInstAvail (st, inum);
		if (!(st->iwin_flags [inum] & IWIN_STORE))
			{
			inum = st->iwin_ldst [inum];
			while (inum >= 0)
				{
				if (st->iwin_flags [inum] & IWIN_STORE) break;
				st->iwin_flags [inum] &= ~IWIN_LDST_DEP;
				CheckInstAvail (st, inum);
				inum = st->iwin_ldst [inum];
				}
			}

		}
#else
		/* For a two phase load/store, check for instructions	*/
		/* that have completed phase one and are ready to go.	*/
		/* Ready = addr valid + predecessors addr valid		*/
		/*	   and ready to issue.				*/
	int	inum;

	for (inum = st->iwin_head_ldst; inum >= 0;
					inum = st->iwin_ldst [inum] )
		{
		    /* Can't issue or move around a load or store	*/
		    /* until we know the address it will use.		*/
		if (!(st->iwin_flags [inum] & IWIN_ADDR_VALID)) break;

		st->iwin_flags [inum] &= ~IWIN_LDST_DEP;
		CheckInstAvail (st, inum);

		    /* If this instruction didn't issue, then done for	*/
		    /* this cycle, try again next time.			*/
		if (!(st->iwin_flags [inum] & IWIN_AVAIL))
			{
			st->iwin_flags [inum] |= IWIN_LDST_DEP;
			break;
			}
		}
#endif
	}


	/*
	 *  ms_lsq  -  Add a load or store request to the load/store buffer
	 *
	 *	Set the status of the entry according to whether it is
	 *	cached/uncached, load/store, ready, conflicting, etc.
	 */

void ms_lsq (struct s_cpu_state *st, int addr, int reg, int reg2,
						int lstype, int inum)
	{
	struct	s_ldst_buffer *entry;
	struct	s_ldst_buffer *store_entry;
	struct	s_lsq	*ls;

	entry = ldst_buffer_alloc (st, st->iwin_paddr [inum], lstype);
	if (entry == NULL)
		{ st->stall_type = ST_LSQ_FULL; st->stall_issue = 1; return; }

	st->inum2ldst[inum] = entry;
	st->iwin_flags[inum] |= IWIN_LDSTBUF;

	ls = entry->ls;
	ls->status = 0;
	ls->lstype = lstype;
	ls->addr = addr;
	ls->paddr = entry->paddr;
	ls->reg = reg;
	ls->reg2 = reg2;
	ls->inum = inum;

	if (st->iwin_flags [inum] & IWIN_UNCACHED)
		ls->status |= LS_ST_UNCACHED;
	else
		{	/* If it is a cached operation, must check for	*/
			/* conflicts with other cached operations.	*/

		if (!IsPrefetch(lstype) && ldst_buffer_conflict (st, entry))
			ls->status |= LS_ST_CONFLICT;
		}

		/* If it's a store, do the operation once in order to	*/
		/* get the valid bytes information set.  Then check	*/
		/* if the value was really available.			*/

	if (IsStore(lstype))
		{
		int	reg_ix;
		REGSTAT	*rs;

		IncStat (ST_NSTORES);

		if (!IsSC(lstype))
			ms_lsop (st, ls, entry, 0);

		reg_ix = st->iwin[inum].r3 >> 1;
		rs = &st->reg_rstat [reg_ix];
		if (rs->reg_status & REG_IN_WIN)
			ls->status |= LS_ST_PEND;

		}

		/* If it's a load, check if it's also waiting for the	*/
		/* value from a store.					*/
	else if (IsLoad(lstype))
		{
		IncStat (ST_NLOADS);

		if (entry->loadhit)
			{
#ifdef LOAD_BYPASS
			store_entry = entry->loadhit;
			if (store_entry->ls->status & LS_ST_PEND)
				ls->status |= LS_ST_PEND;
#else
			ls->status |= LS_ST_PEND;
#endif
			}
		}
	}



	/*
	 *  ms_memory  -  Memory operations.  All of the memory operations,
	 *	whether cached or uncached, have been stored in the load
	 *	store buffer.  This routine checks each cycle which
	 *	operations can be forwarded to the cache.
	 */

void ms_memory (struct s_cpu_state *st)
	{
	int	cache_ops, check_loads, exit_loop;
	struct	s_ldst_buffer *store_entry;
	struct	s_ldst_buffer *entry, *next_entry;
	struct	s_lsq	*ls;

        next_entry = 0; /* Slience bogus compiler error message */

		/* First update the pending flags for the store ops	*/
	check_loads = 0;
	for (entry = st->ldst_head; (entry); entry = next_entry)
		{
		next_entry = entry->next;
		ls = entry->ls;
		if (IsStore(ls->lstype) && (ls->status & LS_ST_PEND))
			{
			int	reg_ix;
			REGSTAT	*rs;

			reg_ix = st->iwin[ls->inum].r3 >> 1;
			rs = &st->reg_rstat [reg_ix];
			if ((rs->reg_status & REG_IN_WIN) == 0)
				{
					/* Turn off LS_ST_CACHED so	*/
					/* it will be retried in cache	*/
				ls->status &= ~(LS_ST_PEND | LS_ST_CACHED);

					/* Call ms_lsop to write the	*/
					/* correct value in the load	*/
					/* store buffer.		*/
				if (!IsSC(ls->lstype))
					ms_lsop (st, ls, ls->ldst_ent, 0);
				check_loads = 1;
				}
			}
		}

		/* Then if a store became available this cycle, check	*/
		/* for waiting loads as well.				*/
#ifdef LOAD_BYPASS
	if (check_loads)
	    {
	    for (entry = st->ldst_head; (entry); entry = next_entry)
		{
		next_entry = entry->next;
		ls = entry->ls;
		if (IsLoad(ls->lstype) && (ls->status & LS_ST_PEND))
			{
			store_entry = entry->loadhit;
			if ((store_entry->ls->status & LS_ST_PEND) == 0)
					/* Turn off LS_ST_CACHED so	*/
					/* it will be retried in cache	*/
				ls->status &= ~(LS_ST_PEND | LS_ST_CACHED);
			}
		}
	    }
#endif

		/* Update the conflict status of entries	*/
	for (entry = st->ldst_head; (entry); entry = next_entry)
		{
		next_entry = entry->next;
		ls = entry->ls;
		if (ls->status & LS_ST_CONFLICT)
			{
			if (!ldst_buffer_conflict (st, entry))
				ls->status &= ~LS_ST_CONFLICT;
			}
		}

		/* The status is up to date, try to send requests	*/
		/* to the cache.					*/
	cache_ops = 0;
	exit_loop = 0;
	for (entry = st->ldst_head; (entry) && (!exit_loop); entry = next_entry)
		{
		next_entry = entry->next;
		ls = entry->ls;
		if (ls->status & LS_ST_DONE) continue;

			/* Send it to the cache if it isn't uncached	*/
			/* and it's never been accepted by the cache	*/
			/* and it doesn't conflict with prior operations */
		if ((ls->status &
		     (LS_ST_UNCACHED | LS_ST_CACHED | LS_ST_CONFLICT)) == 0)
			{
			if (ms_cache (st, ls, entry) >= 0)
				{
					/* The cache has accepted it.	*/
				cache_ops++;
				if (cache_ops >= CACHE_WIDTH) exit_loop = 1;
				}
			}

			/* Uncached operations are handled when the	*/
			/* data is available, and they are no longer	*/
			/* speculative, in the imprecise model. In the	*/
			/* precise model, are handled at graduation.	*/
		else
		if ((ls->status & (LS_ST_UNCACHED | LS_ST_PEND)) ==
							LS_ST_UNCACHED)
			{
#ifdef	PRECISE
			if (st->iwin_headgrad == ls->inum)
#else
			if ((st->iwin_flags[ls->inum] & IWIN_SPEC) == 0)
#endif /* !PRECISE */
				{
                                   entry->dataPtr = (char *) ls->paddr;  /* Mark as active */
                                   if (ms_lsop_uncached (st, ls) == 0) { 
                                      ls->status |= LS_ST_DONE;
                                   }
                                   exit_loop = 1;  /* One uncached per cycle */
				}
			}

			/* If this request was rejected by the cache,	*/
			/* stick here until it is accepted		*/
		if (ls->status & LS_ST_FAILED) exit_loop = 1;
		}

#ifndef PRECISE
	ldst_retire_stores (st);
#endif /* !PRECISE */
	}


	/*
	 *  ldst_buffer_conflict  -  Check starting at the given entry
	 *	in the load/store buffer if there is a potential cache
	 *	conflict between this operation and all prior entries
	 *	in the buffer.  Return TRUE if so.
	 */

static int ldst_buffer_conflict (struct s_cpu_state *st,
					struct s_ldst_buffer *entry)
	{
	struct	s_ldst_buffer *prev_entry;
	struct	s_lsq	*ls;
	int	matched;
	int	new_paddr, new_mask, new_isload;
	struct s_ldst_buffer *new_loadhit;
	int	cacheindex, mask;
	int	i, cmask;
	int	cache_tags [DCACHE_ASSOC];
	int	next_tag, old_tag;

        prev_entry = 0; /* Slience bogus compiler error message */
	ls = entry->ls;
	new_paddr = ls->paddr;
	new_mask = (IsDouble(ls->lstype) ? ~7 : ~3);
	new_isload = IsLoad (ls->lstype);
	new_loadhit = entry->loadhit;

	cache_tags [0] = DCACHE_TAG(new_paddr);
	next_tag = 1;

	matched = 0;
	for (entry = entry->prev; (entry); entry = prev_entry)
		{
		prev_entry = entry->prev;
		ls = entry->ls;
		if (ls->status & LS_ST_UNCACHED)
			continue;	/* Prior request uncached, so	*/
					/* ignore it			*/

			/*
			 * This previous request does not conflict if:
			 *  1) Was to a different cache index
			 *  2) Can't possibly cause a conflict miss replacement
			 *  3) Was to a different word of the line
			 *  4) Both requests are loads
			 *  5) The new request is a load that hits in the
			 *     store buffer
			 */

		cacheindex = DCACHE_INDEXOF(ls->paddr);
		mask = (IsDouble(ls->lstype) ? ~7 : ~3);
		if (cacheindex != DCACHE_INDEXOF(new_paddr))
			continue;

			/* Potential for conflict miss; report match. */
		old_tag = DCACHE_TAG(ls->paddr);
		for (i=0; i<next_tag; i++)
			if (old_tag == cache_tags[i]) break;
		if (i >= next_tag)
			{
			if (next_tag >= DCACHE_ASSOC)
				{
				matched = 1;
				IncStat(ST_LDSTDEP_CONFLICT);
				break;
				}
			cache_tags [next_tag] = old_tag;
			next_tag++;
			continue;
			}

		if (old_tag !=  DCACHE_TAG(new_paddr))
			continue;

		cmask = mask | new_mask;
		if ((ls->paddr&cmask) != (new_paddr&cmask) )
			continue;	/* Different word of same line */

		if (new_isload &&
		    (IsLoad (ls->lstype) || (new_loadhit)) )
			continue;

		matched = 1;
		IncStat(ST_LDSTDEP_FAIL);
		break;
		}
	return (matched);
	}


	/*
	 *  ms_cache  -  Items are pulled from the load/store queue one
	 *		 at a time and processed by this routine.
	 *
	 *	Return -1 if the operation could not be performed
	 */

static int ms_cache (struct s_cpu_state *st, struct s_lsq *ls,
					struct s_ldst_buffer *entry)
	{
	char *dataPtr = NULL;
	int flavor;
	int ret;
	WorkDecls;

	IncStat(ST_CACHE);

		/* Screen out errors due to speculative loads	*/
	if (WouldFault(st, ls->lstype, ls->addr))
		{
		if (IsLoad (ls->lstype))
			st->reg_rstat[ls->reg >> 1].reg_status |= REG_ERROR;
		st->iwin_flags[ls->inum] |= IWIN_FAULT;
		CheckSquash (st, &st->iwin[ls->inum]);
		ls->status |= LS_ST_CACHED;
		return (0);
		}

#ifdef MIPSY_MXS
	if ((ls->lstype == ST_INTEGER_SC) &&
	    !(((CPUState *) (st->mipsyPtr))->LLbit)) {
	    goto  scfail;
	}
	/* Update Mipsy PC so memstat knows where miss came from. */
	((CPUState *) (st->mipsyPtr))->PC = st->iwin_pc[ls->inum];
#endif

    if (ls->lstype == PREFETCH) {
      int mcmd;
      if (ls->paddr != -1) {
         switch (-ls->reg) {
         case 1: case 5: case 7:
            mcmd = MEMSYS_GETX;
            break;
         case 0: case 4: case 6:
         default:
            mcmd = MEMSYS_GET;
            break;
         }
         SCachePrefetch(CPUNUM(st), ls->addr, ls->paddr, mcmd);
      }
#ifdef PREF_DEBUG
        CPUPrint("\t\tCPU %d EX Prefetch addr = %08x cycle = %d ret = %d\n", 
                 CPUNUM(st), entry->ls->paddr, st->work_cycle, ret);
#endif
      free_inst(st, ls->inum);
      ls->status |= LS_ST_DONE;
      return 0;
    }

	if (ls->status & LS_ST_STALL)
		{
		ret = STALL;
		dataPtr = (char *)entry->missTag;
		}
	else
		{
				/* Set flag for CheckIntervention	*/
		ls->status |= LS_ST_FAILED;
		st->ms_action = ACT_DCACHE_MISS;
		if (IsLoad(ls->lstype)) {
		    IncStat(ST_CACHE_LOAD);
		    flavor = (ls->lstype == LD_INTEGER_LL) ? LL_FLAVOR : 0;
		    ret = DCacheFetchShared(CPUNUM(st), ls->addr, ls->paddr,
						flavor, &dataPtr);
		} else {
		    IncStat(ST_CACHE_STORE);
		    flavor = (ls->lstype == ST_INTEGER_SC) ? SC_FLAVOR : 0;
		    ret = DCacheFetchExclusive(CPUNUM(st), ls->addr, ls->paddr,
						flavor, &dataPtr);
		}
		ls->status &= ~LS_ST_FAILED;
		}
	switch (ret) {
	case SUCCESS: {
		/* Hit in the cache, do the operation (unless the data	*/
		/* is still pending).					*/
	    ls->status |= LS_ST_CACHED;
	    if (ls->status & LS_ST_PEND) return (0);

		/* When the operation is done, clear the invalidated	*/
		/* flag.  If the flag gets set between here and when	*/
		/* this operation is retired, then we have to retry it.	*/
	    entry->dataPtr = dataPtr;
	    entry->invalidated = 0;
	    ms_lsop (st, ls, entry, 1);
#ifdef PREF_DEBUG
        CPUPrint("\t\tCPU %d EX %s addr = %08x cycle = %d\n", CPUNUM(st),
                 IsLoad(ls->lstype) ? "Load" : "Store", ls->paddr, st->work_cycle);
#endif
	    ls->status |= LS_ST_DONE;
	    IncStat(ST_CACHE_HIT);
	    return 0;
	}
	case FAILURE: {
	    /* Cache couldn't accept the request. Return failure to caller
	     * so it will be retried.
	     */
	    IncStat(ST_CACHE_FAILURE);
	    if (IsLoad(ls->lstype))
		set_new_excuse (st, ls->reg, ST_CACHE_LBSY);
	    ls->status |= LS_ST_FAILED;
	    return -1;
	}
	case STALL: {
	    /* Memsystem has it now. Wait for callback */
	    ls->status |= LS_ST_STALL + LS_ST_CACHED;
	    entry->missTag = (void *) dataPtr;
            entry->cacheStallReason = MxsClassifyMiss(CPUNUM(st), 
                                     entry->ls->addr, entry->ls->paddr, FALSE);

	    if (ls->status & LS_ST_PEND) return (0);

	    IncStat(ST_CACHE_MISS);
	    if ((entry->loadhit) ||
		(IsStore(ls->lstype) && (ls->lstype != ST_INTEGER_SC))) {
		/* Actually, stores and loads that hit in the write buffer
		 * can be processed. Special case SC instructions. */
		ms_lsop (st, ls, entry, 1);
		ls->status |= LS_ST_DONE;
		if (entry->loadhit) IncStat(ST_CACHE_LOADHIT);
	    }
	    if (IsLoad(ls->lstype))
		set_new_excuse (st, ls->reg, ST_CACHE_BUS);
	    return 0;
	}
	case SCFAILURE: {
	  scfail:
	    Ireg(ls->reg2) = 0;  /* FAIL the SC */
	    if (ls->reg2 == 0)
		reg0_writeback(st, (void *) (ls->inum));
	    else
		reg_writeback(st, (void *) ls->reg2);

	    entry->size = 0;
	    IncStat(ST_CACHE_SCFAILURE);
	    ls->status |= LS_ST_DONE;
	    return 0;
	    }
	default:
	    if (IsLoad(ls->lstype))
		set_new_excuse (st, ls->reg, ST_CACHE_LBSY);
	    ls->status |= LS_ST_CACHED;
	    return (0);
	}
	}



	/*
	 *  set_new_excuse  -  Update the reason why the register is not
	 *			yet available
	 */

static void set_new_excuse (struct s_cpu_state *st, int reg, int excuse)
	{
	int reg_ix = reg >> 1;

	if (st->new_excuse[reg_ix] == ST_NO_EXCUSE)
		st->reg_excuse[reg_ix] = excuse;
	else
		st->new_excuse[reg_ix] = excuse;
	}




/************************************************************************/
/*									*/
/* Common routine to perform load operations, regardless of whether	*/
/* there is a cache or not.						*/
/*									*/
/************************************************************************/

	/*
	 *  ms_lsop  -  Perform load/store operation
	 *
	 *	Converts virtual address to address in simulator's memory
	 *	and performs the indicated operation.  Always returns 0
	 *	to indicate success.
	 */

static int ms_lsop (struct s_cpu_state *st, struct s_lsq *ls,
				struct s_ldst_buffer *entry, int update_inst)
	{
	int  reg, i, update;
	char *dataPtr;
	uint paddr = ls->paddr;
	static double nulldoubleword = 0;
	WorkDecls;

#ifndef MXS_CACHE
		/* If no cache, Must check for errors here:	*/
		/* Screen out errors due to speculative loads	*/
	if (WouldFault(st, lstype, ls->addr))
		{
		if (IsLoad (ls->lstype))
			st->reg_rstat[ls->reg >> 1].reg_status |= REG_ERROR;
		st->iwin_flags[ls->inum] |= IWIN_FAULT;
		CheckSquash (st, &st->iwin[ls->inum]);
		return (0);
		}
#endif

	reg = ls->reg;
	dataPtr = entry->dataPtr;
	if (dataPtr == NULL) {
	    /* This should only happen when we have a read that
	     * hits in the write buffer but is not in the class. Give
	     * a fake memory location to start with load which will
	     * be filled from the write buffer.
	     */
	    dataPtr = (char *) &nulldoubleword;
	}


#if PC_LATENCY > 1
#define WRITEBACKREG() \
	if (reg == 0) \
    Add_to_worklist (st, PC_LATENCY, reg0_writeback,(void *)(ls->inum)); \
	else \
    Add_to_worklist (st, PC_LATENCY, reg_writeback,(void *)reg);
#else
#define WRITEBACKREG() \
	if (reg == 0) reg0_writeback(st,(void *)(ls->inum)); \
	else reg_writeback(st, (void *) reg)
#endif



	switch (ls->lstype)
		{
		case LD_UNSIGNED_B: {
			unsigned char uc;
			uc = * (unsigned char *)dataPtr;
			update =
			ldst_buffer_updateRead(st,entry,paddr,(char *)&uc,1);
			Ureg(reg) = uc;
			WRITEBACKREG();
			break;
		     }
		case LD_UNSIGNED_H: {
			ushort  us;
			us = *(ushort *)dataPtr;
			update =
			ldst_buffer_updateRead(st,entry,paddr,(char *)&us,2);
			Ureg(reg) = us;
			WRITEBACKREG();
			break;
		     }
		case LD_UNSIGNED_L:
			{
			int reg2 = ls->reg2;
			int shft = ((int)dataPtr & 0x03) * 8;

			dataPtr = (char *)((int)dataPtr&0xfffffffc);
			i = *(unsigned int*) dataPtr;
			update = ldst_buffer_updateRead (st, entry,
						paddr &~0x3, (char *)&i, 4);
			Ureg(reg) = Ureg(reg2) & (~(0xffffffff << shft));
			Ureg(reg) |= i << shft;
			WRITEBACKREG();
			break;
			}

		case LD_UNSIGNED_R:
			{
			int reg2 = ls->reg2;
			int shft = (3 - ((int)dataPtr & 0x03)) * 8;
			int mask = 0xffffff00 << (24 - shft);

			dataPtr = (char *)((int)dataPtr&0xfffffffc);
			i = *(unsigned int*) dataPtr;
			update = ldst_buffer_updateRead (st, entry,
						paddr &~0x3, (char *)&i, 4);
			Ureg(reg) = Ureg(reg2) & mask;
			Ureg(reg) |= (i >> shft) & (~mask);
			WRITEBACKREG();
			break;
			}

		case LD_INTEGER_B: {
			signed char c;
			c = *(signed char *) dataPtr;
			update =
			ldst_buffer_updateRead(st,entry,paddr,(char *)&c,1);
			Ireg(reg) = c;
			WRITEBACKREG();
			break;
		     }
		case LD_INTEGER_H: {
			short s;
			s = *(short *) dataPtr;
			update =
			ldst_buffer_updateRead(st,entry,paddr,(char *)&s,2);
			Ireg(reg) = s;

			WRITEBACKREG();
			break;
		     }
		case LD_INTEGER_W: {
			int w;
			w = *(int *) dataPtr;
			update =
			ldst_buffer_updateRead(st,entry,paddr,(char *)&w,4);
			Ireg(reg) = w;

			WRITEBACKREG();
			break;
		     }
		case LD_INTEGER_LL: {
			int w;
			w = *(int *) dataPtr;
			update =
			ldst_buffer_updateRead(st,entry,paddr,(char *)&w,4);
			Ireg(reg) = w;

			WRITEBACKREG();
#ifdef MIPSY_MXS
			((CPUState *) (st->mipsyPtr))->LLbit = 1;
#endif
			break;
		     }
		case LD_FLOAT:{
			float f;
			f = *(float *) dataPtr;
			update =
			ldst_buffer_updateRead(st,entry,paddr,(char *)&f,4);

			Freg(reg) = f;
			WRITEBACKREG();
			break;
		     }
		case LD_DOUBLE: {
			double d;
			d = *(double *) dataPtr;
			update =
			ldst_buffer_updateRead(st,entry,paddr,(char *)&d,8);

			Dreg(reg) = d;
			WRITEBACKREG();
			break;
		     }
		case ST_INTEGER_B: {
			char b = Ireg(ls->reg);
			ldst_buffer_write(st,entry,paddr,(char *)&b,1);
			break;
		     }
		case ST_INTEGER_H: {
			short s = Ireg(ls->reg);
			ldst_buffer_write(st,entry,paddr,(char *)&s,2);
			break;
		     }
		case ST_INTEGER_W: {
			int i = Ireg(ls->reg);
			ldst_buffer_write(st,entry,paddr,(char *)&i,4);
			break;
		     }

		case ST_INTEGER_L: {
			uint i;
			int byte = (((int)paddr) & 0x3);
			i = Ureg(ls->reg);
			ldst_buffer_write(st,entry,paddr,(char *)&i,4-byte);
			break;
		     }
		case ST_INTEGER_R: {
			 uint i;
			int byte = (((int)paddr) & 0x3);
			i = Ureg(ls->reg) << (24 - byte*8);
			ldst_buffer_write(st,entry,paddr&~0x3,(char *)&i,1 + byte);
			break;
		     }
		case ST_FLOAT: {
			float f = Freg(ls->reg);
			ldst_buffer_write(st,entry,paddr,(char *)&f,4);
			break;
		     }
		case ST_DOUBLE: {
			double d = Dreg(ls->reg);
			ldst_buffer_write(st,entry,paddr, (char *)&d,8);
			break;
		     }
		case ST_INTEGER_SC: {
			int i = Ireg(ls->reg);
			reg = ls->reg2;
			ldst_buffer_write(st,entry,paddr,(char *)&i,4);
			Ireg(reg) = 1;

			WRITEBACKREG();
			break;
		     }
        case PREFETCH: {
          fprintf(stderr, "ms_lsop called on prefetch instruction\r\n");
          ms_break (st, NULL, "ERR");
        }
		}

	if (update_inst)
		{
#ifdef DEBUG_CHECKS
		if (st->iwin_flags[ls->inum] & IWIN_SQUASH)
			{
			fprintf (stderr, "Executing squashed load/store\r\n");
			ms_break (st, NULL, "ERR");
			}
#endif /* DEBUG_CHECKS */

#ifdef PRECISE
		if (st->iwin[ls->inum].r1 < 0)
			free_inst(st, ls->inum);
#else /* PRECISE */
		if (IsLoad (ls->lstype))
			{
			int	ret;

			if (update) entry->dataPtr =
						(char *) &nulldoubleword;
			ret = ldst_buffer_retire (st, ls->inum);
#ifdef DEBUG_CHECKS
			if (ret != 0)
				{
				fprintf (stderr, "Retire failure on read\r\n");
				ms_break (st, NULL, "ERR");
				}
#endif /* DEBUG_CHECKS */
			}
#endif /* PRECISE */
		}

	return (0);
	}

int LdSizeOf(int lstype)
{
    switch (lstype)
		{
		case LD_UNSIGNED_B:
		case LD_INTEGER_B:
			return 1;
		case LD_UNSIGNED_H:
		case LD_INTEGER_H:
			return 2;
		case LD_UNSIGNED_L:
			return 4;
		case LD_UNSIGNED_R:
			return 4;
		case LD_INTEGER_W:
		case LD_INTEGER_LL:
		    return 4;
		case LD_FLOAT:
		    return 4;
		case LD_DOUBLE:
		    return 8;
		}
   return 0;
}


	/*
	 *  ldst_buffer_alloc  -  Allocate an entry in ldst_buffer
	 *
	 *	Also check if this is a load that is satisfied by
	 *	an earlier store, and set a pointer to it if so
	 *
	 *	Returns a NULL pointer if allocation fails
	 */

static struct s_ldst_buffer *
ldst_buffer_alloc(struct s_cpu_state *st, int paddr, int lstype)
	{
	struct s_ldst_buffer *entry, *prev_entry, *store1, *store2;
	char *vs;

        prev_entry = 0; /* Slience bogus compiler error message */

		/* Grab the next entry from the reserved list.		*/
		/* It's an error if this entry hasn't been reserved	*/
	entry = st->ldst_nextReserved;
	if (entry == NULL) return (NULL);

		/* Move entry from reserved list to active load/store	*/
		/* list.  Add at end of list to preserve order.		*/
	st->ldst_nextReserved = entry->next;

	if (st->ldst_tail)
		{
		st->ldst_tail->next = entry;
		entry->prev = st->ldst_tail;
		entry->next = NULL;
		st->ldst_tail = entry;
		}
	else
		{
		st->ldst_head = entry;
		st->ldst_tail = entry;
		entry->next = NULL;
		entry->prev = NULL;
		}

		/* Then fill in this entry				*/
	entry->dataPtr = NULL;
	entry->missTag = (void *) -1;
        entry->cacheStallReason = 0;
	entry->paddr = paddr;
	entry->size = 0;
	entry->invalidated = 0;
	entry->loadhit = NULL;
	vs = entry->validBytes;
	vs[0] = 0; vs[1] = 0; vs[2] = 0; vs[3] = 0;
	vs[4] = 0; vs[5] = 0; vs[6] = 0; vs[7] = 0;

		/* If we are allocating a load see if a previous store	*/
		/* can provide us with a value.				*/
	if (IsLoad(lstype))
		{
		int off = (paddr & 7);
		int size = LdSizeOf(lstype);
		int anyhit = 0;
		int b, hitflag;

		store1 = store2 = NULL;
		for (entry = entry->prev; (entry); entry = prev_entry)
			{
			prev_entry = entry->prev;
			if (!IsStore(entry->ls->lstype)) continue;
			if (((entry->paddr)&~7) == (paddr&~7))
				{
				if (store1 == NULL)
					store1 = entry;
				else
					{
					store2 = entry;
					break;
					}
				}
			}
		entry = st->ldst_tail;

	 /*	JEB:  Address and size could be inconsistent at this point,
	  *	due to speculation.  As a later enhancement, detect this
	  *	case and use this as a hint to stop fetching along this
	  *	thread, and activate a different one.  Put the check earlier
	  *	in the pipeline, where the TLB translation is currently.
	  */
		if ((size+off) > 8) size = 8 - off;
		if (store1)
			{
			hitflag = 1;
			for (b = 0; b < size; b++)
				{
				if (store1->validBytes[b+off])
					anyhit = 1;
				else
					{ hitflag = 0; }
				}
			if (hitflag) entry->loadhit = store1;
			if (anyhit) return (entry);
			}

		if (store2)
			{
			hitflag = 1;
			for (b = 0; b < size; b++)
				if (!store2->validBytes[b+off])
					{ hitflag = 0;  break; }
			if (hitflag) entry->loadhit = store2;
			}
		}
	return (entry);
	}


	/*
	 *  ldst_buffer_reserve  -  Reserve an entry in ldst_buffer
	 *
	 *	Returns -1 if reservation fails
	 */

int ldst_buffer_reserve (struct s_cpu_state *st)
	{
	struct s_ldst_buffer *entry;

	entry = st->ldst_nextAvail;
	if (entry)
		{	/* Found a free entry.  Move it to the reserved	*/
			/* list.					*/
		st->ldst_nextAvail = entry->next;

		entry->next = st->ldst_nextReserved;
		st->ldst_nextReserved = entry;
		return (0);
		}
	return (-1);
	}


	/*
	 *  ldst_buffer_release  -  Release a reserved entry
	 */

void ldst_buffer_release (struct s_cpu_state *st)
	{
	struct s_ldst_buffer *entry = st->ldst_nextReserved;
	if (entry)
		{	/* Move entry from reserved list to free list	*/
		st->ldst_nextReserved = entry->next;

		entry->next = st->ldst_nextAvail;
		st->ldst_nextAvail = entry;
		}
#ifdef DEBUG_CHECKS
	else
		{
		fprintf (stderr, "Illegal release of ldst_buffer entry\r\n");
		ms_break (st, NULL, "ERR");
		}
#endif
	}


	/*
	 *  ldst_buffer_free  -  Free the given load store buffer entry
	 */

static void ldst_buffer_free (struct s_cpu_state *st,
					struct s_ldst_buffer *entry)
	{
	struct s_ldst_buffer *scan;

		/* If it's a store, check if any loads are depending	*/
		/* on this value.  Then let them know it is gone.	*/
	if (IsStore (entry->ls->lstype))
		{
		for (scan = st->ldst_head; (scan); scan = scan->next)
			{
			if ((scan->loadhit == entry) &&
			    IsLoad (scan->ls->lstype) )
				{
				scan->loadhit = NULL;
					/* Turn off LS_ST_CACHED so	*/
					/* it will be retried in cache	*/
				scan->ls->status &= ~(LS_ST_PEND|LS_ST_CACHED);
				}
			}
		}

		/* Move the entry from the active list to the free list	*/
	if (entry->prev == NULL)
		st->ldst_head = entry->next;
	else
		entry->prev->next = entry->next;

	if (entry->next == NULL)
		st->ldst_tail = entry->prev;
	else
		entry->next->prev = entry->prev;

	entry->next = st->ldst_nextAvail;
	st->ldst_nextAvail = entry;
	}


	/*
	 *  ldst_buffer_write  -  Write data into the given entry in the
	 *	load/store buffer and mark the set bytes valid.
	 *
	 *	If invalid arguments are passed, it is due to a speculative
	 *	write.  This is OK, just return silently.
	 *
	 *	JEB: As a later enhancement, could use this as a hint to stop
	 *	fetching along this thread, and activate a different one.
	 */

static void ldst_buffer_write(struct s_cpu_state *st,
	struct s_ldst_buffer *entry, int paddr, char *data,int size)
{
   int lineoffset;

   if (size > 8) fprintf(stderr, "Memory op large\r\n");

   entry->paddr = paddr;
   entry->size = size;
   lineoffset = paddr & 7;
   if ((size+lineoffset) > 8) size = 8 - lineoffset;

   switch(size) {
   case 1:
	*(char *) (entry->data + lineoffset) = *(unsigned char*)data;
	*(char *) (entry->validBytes + lineoffset) = 1;
	break;

   case 2:
	*(char *) (entry->data + lineoffset+0) = *(unsigned char*)data;
	*(char *) (entry->data + lineoffset+1) = *(unsigned char*)(data+1);
	*(char *) (entry->validBytes + lineoffset+0) = 1;
	*(char *) (entry->validBytes + lineoffset+1) = 1;
	break;

   case 3:
	*(char *) (entry->data + lineoffset+0) = *(unsigned char*)data;
	*(char *) (entry->data + lineoffset+1) = *(unsigned char*)(data+1);
	*(char *) (entry->data + lineoffset+2) = *(unsigned char*)(data+2);
	*(char *) (entry->validBytes + lineoffset+0) = 1;
	*(char *) (entry->validBytes + lineoffset+1) = 1;
	*(char *) (entry->validBytes + lineoffset+2) = 1;
	break;

   case 4:
	if ((lineoffset & 0x03) != 0) return;
	*(uint  *) (entry->data + lineoffset) = *(unsigned int *)data;
	*(uint  *) (entry->validBytes + lineoffset) =  0x01010101;
	break;

   case 8:
	if ((lineoffset & 0x07) != 0) return;
	*(uint64  *) (entry->data + lineoffset) =
		*(uint64 *) data;
	*(uint64  *) (entry->validBytes + lineoffset) =
	 ((uint64)0x01010101<<32)| (uint64 )0x01010101;
	break;

   default:
	fprintf(stderr, "Memory op invalid size\r\n");
	break;
   }
   return;
}


	/*
	 *  ldst_buffer_updateRead  -  Read data from the given entry to the
	 *	the data area pointed to, if it hit in the store buffer.
	 *
	 *	Returns 1 when the read is satisfied from the store buffer
	 *	Otherwise returns 0.
	 *
	 *	If invalid arguments are passed, it is due to a speculative
	 *	load.  This is OK, just return silently.
	 *
	 *	JEB: As a later enhancement, could use this as a hint to stop
	 *	fetching along this thread, and activate a different one.
	 */

static int
ldst_buffer_updateRead(struct s_cpu_state *st, struct s_ldst_buffer *entry,
			int paddr, char *data, int size)
{
   int lineoffset, i;
   char vb[8];
   struct s_ldst_buffer *store_entry;

   if (entry->loadhit == NULL) return (0);

   vb[0] = vb[1] = vb[2] = vb[3] = vb[4] = vb[5] = vb[6] = vb[7] = 0;
   lineoffset = paddr & 7;
   if ((size+lineoffset) > 8) size = 8 - lineoffset;

				/* Update this entry from the store	*/

   store_entry = entry->loadhit;

   for (i = 0; i < size; i++) {
    if (*(char *) (store_entry->validBytes + lineoffset+i) == 1) {
      data[i] =  *(char *) (store_entry->data + lineoffset+i);
      vb[i+lineoffset] = 1;
      }
   }

   for (i = 0; i < size; i++) {
	lineoffset = paddr & 7;
	if (vb[i+lineoffset] == 0) {
	    /* Didn't update it. */
	    return 0;
	}
   }
   return 1;
}



	/*
	 *  ldst_retire_stores  -  Retire unspeculative stores (for imprecise
	 *		CPU model)
	 */

static void ldst_retire_stores (struct s_cpu_state *st)
	{
	struct	s_ldst_buffer *entry, *next_entry;
	struct	s_lsq	*ls;
	int	inum, ret;
	INST	*ip;

        next_entry = 0; /* Slience bogus compiler error message */
	for (entry = st->ldst_head; (entry); entry = next_entry)
		{
		next_entry = entry->next;
		ls = entry->ls;
		if (IsLoad (ls->lstype) || IsPrefetch(ls->lstype)) continue;
		if ((ls->status & LS_ST_DONE) == 0) continue;

		inum = ls->inum;
		ip = &st->iwin[inum];

			/* Uncached loads don't need any more		*/
			/* processing, just release the entry.		*/
		if (ls->status & LS_ST_UNCACHED)
			{
			if (st->iwin_flags[inum] & IWIN_LDSTBUF)
				{
				st->iwin_flags [inum] &= ~IWIN_LDSTBUF;
				ldst_buffer_free (st, entry);
				}

#ifdef DEBUG_CHECKS
			if (st->iwin_flags[inum] & IWIN_SQUASH)
				{
				fprintf (stderr,
					"Executing squashed load/store\r\n");
				ms_break (st, NULL, "ERR");
				}
#endif /* DEBUG_CHECKS */
			if (ip->r1 > 0)
				reg_writeback ((void *)st, (void *)ip->r1);
			else
				free_inst (st, inum);
			continue;
			}

		if ((st->iwin_flags[inum] & (IWIN_STORE | IWIN_SPEC)) ==
								IWIN_STORE)
			{
			/* Found a store that is no longer speculative,	*/
			/* so process it.				*/
#ifdef DEBUG_CHECKS
			if (st->iwin_flags[inum] & IWIN_SQUASH)
				{
				fprintf (stderr,
					"Executing squashed load/store\r\n");
				ms_break (st, NULL, "ERR");
				}
#endif /* DEBUG_CHECKS */
			ret = ldst_buffer_retire (st, inum);
			if (ret < 0)
					/* Retry the store if the	*/
					/* line has been evicted.	*/
				ls->status &= ~(LS_ST_CACHED | LS_ST_DONE);
			else if (ret == 0)
				{	/* It worked, can free this	*/
					/* instruction.			*/
				if (ip->r1 > 0)
					reg_writeback ((void *)st,
							(void *)ip->r1);
				else
					free_inst (st, inum);
				}
			else
				;	/* Still waiting for the line	*/
					/* to come in, try again next	*/
					/* cycle.			*/
			}
		}
	}


	/*
	 *  ldst_buffer_retire  -  Do actual writes to cache as stores
	 *		graduate.
	 *
	 *	Returns 0 if successful
	 *	Returns 1 if the line hasn't come into the cache yet
	 *	Returns -1 if the line has been evicted (=> need to retry)
	 */

int ldst_buffer_retire(struct s_cpu_state *st, int inum)
{
	struct s_ldst_buffer *entry = st->inum2ldst[inum];
#ifdef DEBUG_CHECKS
	if (st->iwin_flags[inum] & IWIN_SQUASH)
		{
		fprintf (stderr, "Executing squashed load/store\r\n");
		ms_break (st, NULL, "ERR");
		}
#endif /* DEBUG_CHECKS */

   if (entry->ls->inum != inum) {
	fprintf(stderr, "retire failure in ldst_buffer_retire\r\n");
	ms_break (st, NULL, "ERR");
   }
   if (entry->ls->status & LS_ST_UNCACHED) goto retire_exit;
   if (IsPrefetch(entry->ls->lstype)) goto retire_exit;

   if (entry->invalidated) {     /* Line was nuked from the cache */
	char *dataPtr;
	int ret;

	if (IsLoad(entry->ls->lstype) || (entry->ls->lstype == ST_INTEGER_SC)) {
	    IncStat(ST_LDST_INVALIDLOAD);
	    return -1;  /* Fail loads or SCs */
	}
	/* Refetch line for stores. */
	if (entry->dataPtr == NULL) {
	    IncStat(ST_LDST_WAIT);
	    /* Outstanding memory op - must wait for it to finish */
	    return 1;
	}
	st->ms_action = ACT_DCACHE_MISS;
	/* Update Mipsy PC so memstat knows where miss came from. */
	((CPUState *) (st->mipsyPtr))->PC = st->iwin_pc[entry->ls->inum];
	ret = DCacheFetchExclusive(CPUNUM(st), entry->ls->addr,
				entry->ls->paddr,0, &dataPtr);
	switch (ret) {
	case SUCCESS:
	    entry->dataPtr = dataPtr; /* Still in cache */
	    IncStat(ST_LDST_REFETCH);
	    break;
	case FAILURE:
            /* If we got invalidated then most likley we are not in the
             * second level cache.  Make this report as second level Dcache
             * miss. 
             */
            entry->cacheStallReason = E_L2 | E_D; 
	    /* Cache couldn't accept the request */
	    IncStat(ST_LDST_WAIT);
	    return 1;  /* Retry latter. */
	case STALL:
	    /* Memory system has it down */
	    entry->missTag = (void *) dataPtr;
            entry->cacheStallReason = MxsClassifyMiss(CPUNUM(st), 
                                     entry->ls->addr, entry->ls->paddr, FALSE);
	    entry->dataPtr = NULL;
	    entry->invalidated = 0;
	    IncStat(ST_LDST_REFETCH);
	    return 1;
	}
   }
   if ((entry->dataPtr == NULL) &&	/* Data not here yet. */
	(entry->ls->lstype != ST_INTEGER_SC)) { /* OK for failed SCs */
	  IncStat(ST_LDST_WAIT);
	  return 1;
   }

   if (IsStore(entry->ls->lstype)) {
	int off = (entry->paddr&7);
	char *dst = (char *)((uint)entry->dataPtr&~7) + off;
	char *src = entry->data + off;
	IncStat(ST_LDST_RETIRE_STORE);
#ifdef TRACE
	if (tracefile)
		{
		struct	s_trace	trc;

		trc.addr = entry->ls->addr;
		trc.lstype = entry->ls->lstype;
		trc.u.dreg = 0.0;
		bcopy (src, (char *)&trc.u.dreg, entry->size);
		fwrite (&trc, sizeof (struct s_trace), 1, tracefile);
		fflush (tracefile);
		}
#endif
	switch (entry->size) {
	case 0:
	   break;
	case 1:
	  dst[0] = src[0]; break;
	case 2:
	  dst[0] = src[0]; dst[1] = src[1]; break;
	case 3:
	  dst[0] = src[0]; dst[1] = src[1];  dst[2] = src[2]; break;
	case 4:
	  ((int *)dst)[0] = ((int *)src)[0]; break;
	case 8:
	  ((double *)dst)[0] = ((double *)src)[0]; break;
	default:
	   bcopy(src,dst, entry->size);
	}
   } else
	{
	IncStat(ST_LDST_RETIRE_LOAD);
#ifdef TRACE
	if (tracefile)
		{
		struct	s_trace	trc;

		trc.addr = entry->ls->addr;
		trc.lstype = entry->ls->lstype;
		trc.u.dreg = 0.0;
		trc.u.ireg = entry->ls->reg;
		if (!trace_writes)
			{
			fwrite (&trc, sizeof (struct s_trace), 1, tracefile);
			fflush (tracefile);
			}
		}
#endif
	}

retire_exit:
   st->iwin_flags[inum] &= ~IWIN_LDSTBUF;
   ldst_buffer_free (st, entry);
   return (0);
}

/*
 * ldst_record_stall - Record the stall generated by an entry 
 */
void
record_ldst_stall(struct s_cpu_state *st, int inum, int stall)
{
   struct s_ldst_buffer *entry = st->inum2ldst[inum];

   if (entry->ls->inum != inum) {
	fprintf(stderr, "retire failure in ldst_record_stall\r\n");
	ms_break (st, NULL, "ERR");
   }
   MS_STALL_EVENT(CPUNUM(st), entry->ls->addr, st->iwin_pc[inum], 
                  stall, entry->cacheStallReason);
}

void
record_icache_stall(struct s_cpu_state *st, int pc, int stall)
{
   MS_STALL_EVENT(CPUNUM(st), pc, pc, stall, 
                  st->active_thread->icache_stall_reason);

}

void
record_pipeline_stall(struct s_cpu_state *st, int pc, int stall)
{
   MS_STALL_EVENT(CPUNUM(st), pc, pc, stall, E_PIPELINE);
}
	/*
	 *  ldst_buffer_squash
	 */

void ldst_buffer_squash(struct s_cpu_state *st, int inum)

{
   struct s_ldst_buffer *entry = st->inum2ldst[inum];

   if (entry->ls->inum != inum) {
	fprintf(stderr, "retire failure in ldst_buffer_squash\r\n");
	ms_break (st, NULL, "ERR");
   }
   IncStat(ST_LDST_BUF_SQUASH);
   if (entry->dataPtr == NULL)
	IncStat(ST_LDST_BUF_SQUASH_ACT);
   st->iwin_flags[inum] &= ~IWIN_LDSTBUF;
   ldst_buffer_free (st, entry);
   return;
}


/*
 * MxsApproveImiss - Return TRUE if it is safe to process an instruction
 *		   cache miss to this address. This routine will disallow
 *		   any instruction cache miss that might invalidate an active
 *		   entry in the ldst buffer.
 */
int
MxsApproveImiss(struct s_cpu_state *st,int paddr)
{

   int sind;
   struct s_ldst_buffer *entry;

   sind = SCACHE_INDEXOF(paddr);
   for (entry = st->ldst_head; (entry); entry = entry->next)
	{
	if (SCACHE_INDEXOF(entry->paddr) != sind)
	 continue;  /* Skip if not an active entry at same Scache index */
	return 0;
   }
   return 1;
}


	/*
	 *  DoMxsIntervention  -  When a cache line is thrown out, notify
	 *			  the load/store buffer by calling this
	 *			  routine.
	 */
void
DoMxsIntervention(struct s_cpu_state *st, int paddr, int size, int writebackonly)
{
    struct s_ldst_buffer *entry;
    int paddr_end = paddr + size;

    for (entry = st->ldst_head; (entry); entry = entry->next)
	{
	if (entry->dataPtr == NULL) continue; /* Only a problem if we have
						 returned data */

	if ((entry->paddr >= paddr) && (entry->paddr < paddr_end)) {
	    if (!writebackonly || IsStore(entry->ls->lstype)) {
		entry->invalidated = 1;
	    }
	}
    }
}


	/*
	 *  CheckIntervention  -  Check if recycling the cache line might cause
	 *			  an intervention, and if so return TRUE.
	 *
	 *	When mtag is specified, stop the check when the entry
	 *	containing that miss tag is reached.
	 */

int CheckIntervention (struct s_cpu_state *st, void *mtag, int paddr, int size)
	{
	struct s_ldst_buffer *entry;
	int paddr_end = paddr + size;
	int	ignore_null = 0;

	for (entry = st->ldst_head; (entry); entry = entry->next)
		{
			/* After the first failed entry is encountered,	*/
			/* just need to worry about entries with non-	*/
			/* null data pointers.				*/
		if (entry->ls->status & LS_ST_FAILED) ignore_null = 1;
		if (ignore_null && (entry->dataPtr == NULL)) continue;

		if (mtag && (entry->missTag == mtag)) return (0);
		if ((entry->paddr >= paddr) && (entry->paddr < paddr_end))
			return (1);
		}
	return (0);
	}



	/*
	 *  GetMxsAction  -  Pass the saved action to caller
	 */

int GetMxsAction (struct s_cpu_state *st)
	{
	return (st->ms_action);
	}


	/*
	 *  DoMxsAction  -  Perform the requested action in response to
	 *		    a memory system request.
	 */

void DoMxsAction (struct s_cpu_state *st, void *missTag, int ms_action)
	{
	struct	s_ldst_buffer *entry, *next_entry = 0;

	switch (ms_action)
		{
		case ACT_UNSTALL_ICACHE:
			recurse_unstall (st, 0);
			return;
		case ACT_DCACHE_MISS:
			{
			for (entry = st->ldst_head; (entry); entry = next_entry)
			    {
			    next_entry = entry->next;
			    if (entry->missTag == missTag)
				{    /* Found the corresponding entry	*/
				     /* in the load/store buffer	*/
				struct s_lsq *ls = entry->ls;

				entry->missTag = (void *) -1;
				ls->status &= ~LS_ST_STALL;
				if (ls->status & LS_ST_DONE)
				    {	/* In this case, the operation	*/
					/* has been performed in the	*/
					/* load/store buffer already.	*/
				    Result ret;
				    char *dataPtr;

				     /* Update Mipsy PC so memstat knows 
                                      * where miss came from. */
				     ((CPUState *) (st->mipsyPtr))->PC = 
                                        st->iwin_pc[ls->inum];
				    if (IsLoad(ls->lstype))
					ret = DCacheFetchShared(CPUNUM(st),
					     ls->addr, ls->paddr,0, &dataPtr);
				    else
					ret = DCacheFetchExclusive(CPUNUM(st),
					     ls->addr, ls->paddr,0, &dataPtr);
				    if (ret != SUCCESS)
					{
					fprintf(stderr,
					  "Cache callback messup\r\n");
					ms_break (st, NULL, "ERR");
					}
				    entry->dataPtr = dataPtr;
				    }
				else
				    ls->status &= ~LS_ST_CACHED;
				}
			    }
			recurse_unstall (st, 0);  /* Just in case the icache
						   * miss merged with a dcache
			return;			   * miss */
			}
		default:
			return;
		}

	}

static int ms_lsop_uncached (struct s_cpu_state *st, struct s_lsq *ls)
	{
	uint	data_address;
	int	i;
        int err;
#undef WRITEBACKREG
#if UC_LATENCY > 1
#define WRITEBACKREG() \
	if (ls->reg == 0) \
    Add_to_worklist (st, UC_LATENCY, reg0_writeback,(void *)(ls->inum)); \
	else \
    Add_to_worklist (st, UC_LATENCY, reg_writeback,(void *)ls->reg);
#else
#define WRITEBACKREG() \
	if (ls->reg == 0) reg0_writeback(st,(void *)(ls->inum)); \
	else reg_writeback(st, (void *) ls->reg)
#endif

        err = 0;
	switch (ls->lstype)
		{
		case LD_UNSIGNED_B: {
                        unsigned char c;
                        err = DoUncachedRead(st,ls->addr, ls->paddr, 1, &c);
                        if (err == 0) { 
                           Ureg(ls->reg) = c;
                           WRITEBACKREG();
                        } 
			break;
                }
		case LD_UNSIGNED_H: {
                        unsigned short h;
                        err = DoUncachedRead(st,ls->addr,ls->paddr, 2, &h);
                        if (err == 0) { 
                           Ureg(ls->reg) = h;
                           WRITEBACKREG();
                        } 
			break;
                }
		case LD_UNSIGNED_L:
			{
			int shft = ((int)ls->paddr & 0x03) * 8;
			data_address = ((uint)ls->paddr&0xfffffffc);
                        err = DoUncachedRead(st,ls->addr,data_address, 4, &i);
                        if (err == 0) { 
                           Ureg(ls->reg) = Ureg(ls->reg2) &
						(~(0xffffffff << shft));
                           Ureg(ls->reg) |= i << shft;
                           WRITEBACKREG();
                        }
			break;
			}

		case LD_UNSIGNED_R:
			{
			int shft = (3 - ((int)ls->paddr & 0x03)) * 8;
			int mask = 0xffffff00 << (24 - shft);
			data_address = ((uint)ls->paddr&0xfffffffc);
                        err = DoUncachedRead(st,ls->addr,data_address, 4, &i);
                        if (err == 0) { 
                           Ureg(ls->reg) = Ureg(ls->reg2) & mask;
                           Ureg(ls->reg) |= (i >> shft) & (~mask);
                           WRITEBACKREG();
                        }
			break;
			}

		case LD_INTEGER_B: {
                        signed char b;
                        err = DoUncachedRead(st,ls->addr,ls->paddr, 1, &b);
                        if (err == 0) { 
                           Ireg(ls->reg) = b;
                           WRITEBACKREG();
                        } 
			break;
                }
		case LD_INTEGER_H: {
                        short h;
                        err = DoUncachedRead(st,ls->addr,ls->paddr, 2, &h);
                        if (err == 0) { 
                           Ireg(ls->reg) = h;
                           WRITEBACKREG();
                        } 
			break;
                }
		case LD_INTEGER_W:
			if (ls->addr & 1) {
			    int retval;
			    int addr = ls->addr & ~1;

			    /* Turn the lw t0, 1(a0) instruction into a conditional
			     * store */
			    if ((*(int *)addr) & 1) {
				retval = 0;
			    }  else {
				(*(int *)addr) = (int) 1;
				retval = 1;
			    }
			    Ireg(ls->reg) = retval;
			    WRITEBACKREG();
                            err = 0;
			    break;
			}
                        err = DoUncachedRead(st,ls->addr,ls->paddr, 4, &i);

                        if (err == 0) { 
                           Ireg(ls->reg) = i;
                           WRITEBACKREG();
                        } 
			break;

		case LD_FLOAT: {
                        float f;
                        err = DoUncachedRead(st,ls->addr,ls->paddr, 4, &f);
                        if (err == 0) { 
                           Freg(ls->reg) = f;
                           WRITEBACKREG();
                        } 
			break;
                }
		case LD_DOUBLE: {
                        double d;
                        err = DoUncachedRead(st,ls->addr,ls->paddr, 8, &d);
                        if (err == 0) { 
                           Dreg(ls->reg) = d;
                           WRITEBACKREG();
                        } 
			break;
                }
		case ST_INTEGER_B: {
                        char b = (char) Ireg(ls->reg);
                        err = DoUncachedWrite(st,ls->addr,ls->paddr, 1, 0, &b);
			break;
                }
                case ST_INTEGER_H: {
                        short h = (short) Ireg(ls->reg);
                        err = DoUncachedWrite(st,ls->addr,ls->paddr, 2, 0, &h);
			break;
                }

		case ST_INTEGER_W:
                        err = DoUncachedWrite(st,ls->addr,ls->paddr, 4, 0, &Ireg(ls->reg));
			break;

		case ST_FLOAT:
                        err = DoUncachedWrite(st,ls->addr,ls->paddr, 4, 0, &Freg(ls->reg));
			break;

		case ST_DOUBLE:
                        err = DoUncachedWrite(st,ls->addr,ls->paddr, 8, 0, &Dreg(ls->reg));
			break;

		case ST_INTEGER_L:
		case ST_INTEGER_R:
                   /* Can't handle these yet */
		default:
			fprintf(stderr,
				"Bad lstype passed to ms_lsop_uncached\r\n");
			ms_break (st, NULL, "ERR");
			break;
		}

        if (err != 0) {
           return err;
        }
	if (IsStore(ls->lstype)) {
	    IncStat(ST_LSOP_UNCACHED_STORE);
#ifdef PRECISE
#ifdef DEBUG_CHECKS
	    if (st->iwin_flags[ls->inum] & IWIN_FREED)
		{
		fprintf(stderr, "Freed store instruction being executed!\r\n");
		ms_break (st, NULL, "ERR");
		}
#endif /* DEBUG_CHECKS */
#endif
	    free_inst(st, ls->inum);
	} else
	    IncStat(ST_LSOP_UNCACHED_LOAD);
        return err;
	}



	/*
	 *  recurse_unstall  -  Unstall the fetch unit after a cache miss
	 *			has been satisfied.
	 *
	 *	Return TRUE if a thread was unstalled.
	 */

static int recurse_unstall (struct s_cpu_state *st, int br_node)
	{
	BrTREE	*br;
	THREAD	*th;
	int ret = 0;
	if (br_node < 0) return (0);

	br = &st->branch_tree[br_node];
	th = &st->threads[br->thread];
	if (th->stall_icache)
		{
		th->stall_icache = 0;
		UpdateStallFetch (th);
		ret = 1;
		}

	return (ret + recurse_unstall (st, br->lchild) +
			recurse_unstall (st, br->rchild));
	}


#ifndef MIPSY_MXS
	/*
	 *  is_misaligned  -  Return TRUE if the load/store instruction
	 *			will cause an alignment error.
	 */

static int is_misaligned (int lstype, int addr)
	{
	switch (lstype)
		{
		case LD_UNSIGNED_B:
			return (0);

		case LD_UNSIGNED_H:
			return (addr & 0x01);

		case LD_UNSIGNED_L:
			return (0);

		case LD_UNSIGNED_R:
			return (0);

		case LD_INTEGER_B:
			return (0);

		case LD_INTEGER_H:
			return (addr & 0x01);

		case LD_INTEGER_W:
			return (addr & 0x03 ? 1 : 0);

		case LD_FLOAT:
			return (addr & 0x03 ? 1 : 0);

		case LD_DOUBLE:
			return (addr & 0x07 ? 1 : 0);

		case ST_INTEGER_B:
			return (0);

		case ST_INTEGER_H:
			return (addr & 0x01);

		case ST_INTEGER_W:
			return (addr & 0x03 ? 1 : 0);

		case ST_INTEGER_L:
			return (0);

		case ST_INTEGER_R:
			return (0);

		case ST_FLOAT:
			return (addr & 0x03 ? 1 : 0);

		case ST_DOUBLE:
			return (addr & 0x07 ? 1 : 0);
                default:
                        break;
		}
	return (1);
	}
#endif /* !MIPSY_MXS */