#!/bin/csh -f
#
#  Shell script for generating tabular trace file 
#
#  Usage: do_sim <test>
#
#
#  12/30/94   TD
#

if ( $#argv != 1 ) then
  echo "Usage: $0 <test>"
  exit
endif

vlsishell << EOF
set echo on

####################################
# invoke qsim and load netlist
####################################
qsim

mode compassqsim
simparms transistorDelay 0.1
#switch [swt]rcp_qsim

select model pc3cl3
select model pc3cl3w

#load [nls]rcp_f
load (pipe) [nls]rcp_f_wst

####################################
# setup environment
####################################
radix 16
options bidirConflict
options failTestOnZ
#trace (static, tabular)
options tabularReportOnChange
trace (dynamic, tabular)
#trace (dynamic)

####################################
# rambus pullup resistors
####################################
#transistor P vss bus_enable_rac vdd
#transistor P vss bus_ctrl_rac vdd
#transistor P vss bus_data_rac[8] vdd
#transistor P vss bus_data_rac[7] vdd
#transistor P vss bus_data_rac[6] vdd
#transistor P vss bus_data_rac[5] vdd
#transistor P vss bus_data_rac[4] vdd
#transistor P vss bus_data_rac[3] vdd
#transistor P vss bus_data_rac[2] vdd
#transistor P vss bus_data_rac[1] vdd
#transistor P vss bus_data_rac[0] vdd

####################################
# display current environment
####################################
#preprocess
simparms
options
trace
modeloptions

####################################
# bus and signal aliases
####################################
vector vbus_data_pad[6:0]
vector sys_ad_pad[31:0]
vector sys_cmd_pad[4:0]
vector ad16_data_pad[15:0]

equiv sys_ad_enable_l[0]   sys_ad_pad_oen
equiv sys_ad_enable_l[0]   sys_cmd_pad_oen
equiv tst_ad16_enable_l[0] ad16_data_pad_oen
equiv vclk_enable_l        vclk_pad_oen

equiv bus_ctrl_rac bus_ctrl_rac_i
equiv bus_ctrl_rac bus_ctrl_rac_o

equiv bus_data_rac[8] bus_data_rac_i[8]
equiv bus_data_rac[7] bus_data_rac_i[7]
equiv bus_data_rac[6] bus_data_rac_i[6]
equiv bus_data_rac[5] bus_data_rac_i[5]
equiv bus_data_rac[4] bus_data_rac_i[4]
equiv bus_data_rac[3] bus_data_rac_i[3]
equiv bus_data_rac[2] bus_data_rac_i[2]
equiv bus_data_rac[1] bus_data_rac_i[1]
equiv bus_data_rac[0] bus_data_rac_i[0]

vector bus_data_rac[8:0]
vector bus_data_rac_o[8:0] bus_data_rac[8:0]

####################################
# list signals to be dumped in trace file
####################################
#watch tx_clk                  
#
#watch reset_l_pad             
#watch test_pad                
#watch p_valid_pad             
#watch v_ref                   
#watch c_ctl_pgm               
#watch pif_rsp_pad             
## 
#watch mclock_pad              
#watch e_valid_pad             
#watch e_ok_pad                
#watch int_pad                 
#watch rx_clk                  
#watch ad16_aleh_pad           
#watch ad16_alel_pad           
#watch ad16_read_pad           
#watch ad16_write_pad          
#watch pif_cmd_pad             
#watch pif_clock_pad           
#watch abus_data_pad           
#watch abus_word_pad           
#watch abus_clock_pad          
#watch vbus_data_pad
#watch vbus_sync_pad           
##
#watch sys_ad_pad
#watch sys_ad_pad_oen          
#watch sys_cmd_pad
#watch sys_cmd_pad_oen         
#watch ad16_data_pad
#watch ad16_data_pad_oen       
#watch vclk_pad                
#watch vclk_pad_oen            
## rambus interface
#watch bus_enable_rac          
#watch bus_ctrl_rac
#watch bus_data_rac[8:0]

# vi debug
#vector vi_0.cbus_select[1:0]
#vector vi_0.cbus_command[2:0]
#vector vi_0.dbus_data[63:0]
#vector vi_0.ebus_data[7:0]
#vector vi_0.vbus_data[6:0]
#vector vi_0.cbus_data[31:0]

#watch vi_0.clk
#watch vi_0.vclk
#watch vi_0.reset_l
#watch vi_0.cbus_read_enable
#watch vi_0.cbus_write_enable
#watch vi_0.cbus_select
#watch vi_0.cbus_command
#watch vi_0.dma_start
#watch vi_0.dma_last
#watch vi_0.dma_grant
#watch vi_0.read_grant
#watch vi_0.dbus_data
#watch vi_0.ebus_data
#watch vi_0.dma_request
#watch vi_0.read_request
#watch vi_0.vbus_data
#watch vi_0.vbus_sync
#watch vi_0.vbus_clock_enable_l
#watch vi_0.vi_int
#watch vi_0.refresh_strobe
#watch vi_0.cbus_data
#watch vi_0.cbus_write_enable

# tst debug
#watch tst_0.clock
#watch tst_0.pad_reset_l
#watch tst_0.test
#vector tst_0.ad16_data_in[14:0]
#watch tst_0.ad16_data_in
#watch tst_0.ad16_enable_l
#watch tst_0.ad16_read_l
#watch tst_0.ad16_write_l
#watch tst_0.bist_flag
#watch tst_0.tst_ad16_enable_l_0
#watch tst_0.tst_ad16_enable_l_1
#watch tst_0.tst_ad16_read_l
#watch tst_0.tst_ad16_write_l
#watch tst_0.tst_by_pass
#watch tst_0.tst_bist_mode
#watch tst_0.tst_iost_mode
#watch tst_0.tst_rac_reset
#watch tst_0.tst_ext_be
#watch tst_0.tst_c_ctl_en
#vector tst_0.tst_c_ctl_i[5:0]
#watch tst_0.tst_c_ctl_i
#watch tst_0.tst_c_ctl_ld
#watch tst_0.tst_synclk_set
#watch tst_0.tst_pwr_up
#watch tst_0.tst_idd_test
#watch tst_0.tst_reset_l_0
#watch tst_0.tst_reset_l_1
#watch tst_0.tst_reset_l_2
#watch tst_0.tst_reset_l_3
#watch tst_0.tst_reset_l_4
#watch tst_0.tst_reset_l_5
#watch tst_0.tst_reset_l_6
#watch tst_0.tst_reset_l_7
#watch tst_0.tst_reset_l_8
#watch tst_0.tst_reset_l_9
#
## pi debug
##vector pi_0.cbus_select[1:0]
##vector pi_0.cbus_command[2:0]
##vector pi_0.ad16_data_in[15:0]
##vector pi_0.ad16_data_out[15:0]
##vector pi_0.cbus_data[31:0]
#vector pi_0.dbus_data[63:0]
#
#watch pi_0.clock
#watch pi_0.reset_l
#watch pi_0.cbus_read_enable
#watch pi_0.cbus_write_enable
#watch pi_0.cbus_select
#watch pi_0.cbus_command
#watch pi_0.dma_start
#watch pi_0.dma_last
#watch pi_0.dbus_enable
#watch pi_0.dma_grant
#watch pi_0.read_grant
#watch pi_0.ad16_data_in
#watch pi_0.dma_request
#watch pi_0.read_request
#watch pi_0.pi_interrupt
#watch pi_0.ad16_aleh
#watch pi_0.ad16_alel
#watch pi_0.ad16_read_l
#watch pi_0.ad16_write_l
#watch pi_0.ad16_enable_l
#watch pi_0.ad16_data_out
#watch pi_0.cbus_data
#watch pi_0.cbus_write_enable
#watch pi_0.dbus_data
#watch pi_0.dbus_enable 
#
## mi debug
##vector sys_ad_in_h[31:0]     
##vector sys_cmd_in_h[4:0]    
##vector cbus_select[1:0]    
##vector cbus_command[2:0]  
#vector version[31:0]     
#vector sys_ad_out_h[31:0]     
#vector sys_cmd_out_h[4:0]    
#vector cbus_data[31:0]      
#vector dbus_data[63:0]     
#vector ebus_data[7:0]     
#
#watch clock
#watch reset_l
#watch cbus_read_enable
#watch cbus_write_enable
#watch cbus_grant
#watch dbus_read_enable
#watch dbus_write_enable
#watch dma_start
#watch dma_last
#watch sys_ad_in_h
#watch sys_cmd_in_h
#watch p_valid_l
#watch cbus_select
#watch cbus_command
#watch pi_interrupt
#watch vi_interrupt
#watch ai_interrupt
#watch si_interrupt
#watch sp_interrupt
#watch pipe_busy
#watch version
#watch cbus_data
#watch dbus_data
#watch ebus_data
#watch dma_request
#watch write_request
#watch read_request
#watch sys_ad_out_h
#watch sys_cmd_out_h
#watch e_valid_l
#watch e_ok_l
#watch int_l
#watch sys_ad_enable_l
#
# if_block debug
#watch reset_l
#vector if_logic.cbus_select[1:0]
#watch if_logic.cbus_select
#vector if_logic.dbus_data[63:0]
#watch if_logic.dbus_data
#vector if_logic.sys_cmd_in[4:0]
#watch if_logic.sys_cmd_in
#vector if_logic.cbus_data[31:0]
#watch if_logic.cbus_data
#vector if_logic.sys_ad_in[31:0]
#watch if_logic.sys_ad_in
#vector if_logic.sys_ad_enable_l[4:0]
#watch if_logic.sys_ad_enable_l
#vector if_logic.sys_cmd_out[4:0]
#watch if_logic.sys_cmd_out
#vector if_logic.cbus_command[2:0]
#watch if_logic.cbus_command
#vector if_logic.sys_ad_out[31:0]
#watch if_logic.sys_ad_out
#vector if_logic.ebus_data[7:0]
#watch if_logic.ebus_data
#watch if_logic.clock
#watch if_logic.reset_l_0
#watch if_logic.dma_start
#watch if_logic.vclk
#watch if_logic.si_dbus_write_enable
#watch if_logic.pif_rsp
#watch if_logic.mi_dbus_read_enable
#watch if_logic.mi_dbus_write_enable
#watch if_logic.dma_last
#watch if_logic.p_valid_l
#watch if_logic.pi_interrupt
#watch if_logic.vi_interrupt
#watch if_logic.sp_interrupt
#watch if_logic.pipe_busy
#watch if_logic.scan_en
#watch if_logic.by_p_sel
#watch if_logic.dma_ready
#watch if_logic.sp_dma_request
#watch if_logic.sp_read_request
#watch if_logic.mem_read_request
#watch if_logic.cmd_dma_request
#watch if_logic.cmd_read_request
#watch if_logic.ri_read_request
#watch if_logic.pi_dma_request
#watch if_logic.pi_read_request
#watch if_logic.vi_dma_request
#watch if_logic.vi_read_request
#watch if_logic.span_dma_request
#watch if_logic.span_read_request
#watch if_logic.refresh_strobe
#watch if_logic.abus_data
#watch if_logic.abus_word
#watch if_logic.abus_clock
#watch if_logic.pif_cmd
#watch if_logic.pif_clock
#watch if_logic.e_valid_l
#watch if_logic.e_ok_l
#watch if_logic.int_l
#watch if_logic.sp_cbus_read_enable
#watch if_logic.sp_cbus_write_enable
#watch if_logic.sp_dma_grant
#watch if_logic.sp_read_grant
#watch if_logic.mem_cbus_write_enable
#watch if_logic.cmd_cbus_read_enable
#watch if_logic.cmd_cbus_write_enable
#watch if_logic.cmd_dma_grant
#watch if_logic.cmd_read_grant
#watch if_logic.ri_cbus_read_enable
#watch if_logic.ri_cbus_write_enable
#watch if_logic.ri_read_grant
#watch if_logic.pi_cbus_read_enable
#watch if_logic.pi_cbus_write_enable
#watch if_logic.pi_dma_grant
#watch if_logic.pi_read_grant
#watch if_logic.vi_cbus_read_enable
#watch if_logic.vi_cbus_write_enable
#watch if_logic.vi_dma_grant
#watch if_logic.vi_read_grant
#watch if_logic.span_cbus_read_enable
#watch if_logic.span_cbus_write_enable
#watch if_logic.span_dma_grant
#watch if_logic.span_read_grant

# rac i/o
#watch rac_0.BusClk
#vector rac_0.BDSel[3:0] 
#watch rac_0.BDSel
#vector rac_0.BCSel[3:0] 
#watch rac_0.BCSel
#vector rac_0.BESel[3:0] 
#watch rac_0.BESel
#vector rac_0.RDSel[3:0] 
#watch rac_0.RDSel
#vector rac_0.RCSel[3:0]
#watch rac_0.RCSel
#watch rac_0.Reset
#vector rac_0.TData7[10:0] 
#watch rac_0.TData7
#vector rac_0.TData6[10:0] 
#watch rac_0.TData6
#vector rac_0.TData5[10:0] 
#watch rac_0.TData5
#vector rac_0.TData4[10:0] 
#watch rac_0.TData4
#vector rac_0.TData3[10:0] 
#watch rac_0.TData3
#vector rac_0.TData2[10:0] 
#watch rac_0.TData2
#vector rac_0.TData1[10:0] 
#watch rac_0.TData1
#vector rac_0.TData0[10:0]
#watch rac_0.TData0
#watch rac_0.Vref
#watch rac_0.BISTMode
#watch rac_0.IOSTMode
#watch rac_0.SCANMode
#watch rac_0.SCANClk
#watch rac_0.SCANEn
#watch rac_0.SCANIn
#watch rac_0.SynClkIn
#watch rac_0.CCtlEn
#watch rac_0.CCtlLd
#vector rac_0.CCtlI[5:0]
#watch rac_0.CCtlI
#watch rac_0.CCtlPgm
#watch rac_0.PwrUp
#watch rac_0.ExtBE
#watch rac_0.StopR
#watch rac_0.StopT
#watch rac_0.ByPass
#watch rac_0.ByPSel
#watch rac_0.rclkASIC
#watch rac_0.tclkASIC
#watch rac_0.PhStall
 

#vector rac_0.RData7[9:0] 
#watch rac_0.RData7
#vector rac_0.RData6[9:0] 
#watch rac_0.RData6
#vector rac_0.RData5[9:0] 
#watch rac_0.RData5
#vector rac_0.RData4[9:0] 
#watch rac_0.RData4
#vector rac_0.RData3[9:0] 
#watch rac_0.RData3
#vector rac_0.RData2[9:0] 
#watch rac_0.RData2
#vector rac_0.RData1[9:0] 
#watch rac_0.RData1
#vector rac_0.RData0[9:0]
#watch rac_0.RData0
#watch rac_0.SynClk
#watch rac_0.SynClkFd
#watch rac_0.BusEnable
#watch rac_0.BISTFlag
#watch rac_0.SCANOut
##vector rac_0.CCtlO[5:0]
##watch rac_0.CCtlO
##watch rac_0.ASynIn
##watch rac_0.ASynOut
##watch rac_0.Transmit

#watch rac_0.BusCtrl
#vector rac_0.BusData[8:0]
#watch rac_0.BusData


## super-synchronous
##watch tx_clk
#
##watch reset_l_pad
##watch test_pad
##watch p_valid_pad
##watch v_ref
##watch c_ctl_pgm
##watch pif_rsp_pad
##
##watch mclock_pad
##watch e_valid_pad
##watch e_ok_pad
##watch int_pad
##watch rx_clk
##watch ad16_aleh_pad
##watch ad16_alel_pad
##watch ad16_read_pad
##watch ad16_write_pad
##watch pif_cmd_pad
##watch pif_clock_pad
##watch abus_data_pad
##watch abus_word_pad
##watch abus_clock_pad
##watch vbus_data_pad
##watch vbus_sync_pad
##
##watch sys_ad_pad
##watch sys_ad_enable_l[3]
##watch sys_ad_enable_l[2]
##watch sys_ad_enable_l[1]
##watch sys_ad_enable_l[0]
#
##watch sys_cmd_pad
#
##watch ad16_data_pad
##watch tst_ad16_enable_l[1]
##watch tst_ad16_enable_l[0]
#
##watch vclk_pad
##watch vclk_enable_l
#
## rambus interface
##watch bus_enable_rac
##watch bus_ctrl_rac
##watch bus_data_rac[8:0]
#
# si i/o
#if_logic.\si_0/pchclk
#if_logic.\si_0/div_cnt[1:0]
#if_logic.\si_0/si_pchclk_0/reset_l_d1
#if_logic.\si_0/n91

# debug
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_1_*
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_1_.q
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_1_.qn
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_1_.d
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_1_.cp
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_1_.cdn
#
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_0_*
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_0_.q
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_0_.qn
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_0_.d
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_0_.cp
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_0_.cdn
#
##watch if_logic.si_0/si_pchclk_0*
#
##watch syn_clk
##watch pad_0/syn_clkbot
##watch pad_0/syn_clk0
##watch pad_0/syn_clk1
##watch clock
##watch if_logic.clock
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_0_.CP
##watch if_logic.si_0/si_pchclk_0/div_cnt_reg_1_.CP

# clock buffer debug
##watch pad_0/IOpad014.cclk
##watch pad_0/IOpad014.e
##watch pad_0/IOpad014.cp

#
##watch pad_0/IOpad109.cclk
##watch pad_0/IOpad109.e
##watch pad_0/IOpad109.cp

##watch pad_0/syn_clktop
##watch syn_clk

# debug
#watch rdp_0/cs_ew_cv.clk
#watch rdp_0/cs_ew_cv.gclk
#watch rdp_0/cs_ew_cv.reset_l
#vector rdp_0/cs_ew_cv.xbus_cs_data[63:0]
#watch rdp_0/cs_ew_cv.xbus_cs_data
#watch rdp_0/cs_ew_cv.xbus_cs_valid

# io_ri
#vector io_ri.cbus_select[1:0]
#watch io_ri.cbus_select
#vector io_ri.cp0_address[2:0]
#watch io_ri.cp0_address
#vector io_ri.cp0_data[31:0]
#watch io_ri.cp0_data
#vector io_ri.r_data_1[0:8]
#watch io_ri.r_data_1
#vector io_ri.mem_write_data[63:0]
#watch io_ri.mem_write_data
#vector io_ri.r_data_0[9:0]
#watch io_ri.r_data_0
#vector io_ri.r_data_6[0:8]
#watch io_ri.r_data_6
#vector io_ri.r_data_7[0:8]
#watch io_ri.r_data_7
#vector io_ri.rbus_data_out[63:0]
#watch io_ri.rbus_data_out
#vector io_ri.dbus_data[63:0]
#watch io_ri.dbus_data
#vector io_ri.xbus_data[63:0]
#watch io_ri.xbus_data
#vector io_ri.cbus_data[31:0]
#watch io_ri.cbus_data
#vector io_ri.mem_address[8:0]
#watch io_ri.mem_address
#vector io_ri.pc_data[9:0]
#watch io_ri.pc_data
#vector io_ri.r_data_2[0:8]
#watch io_ri.r_data_2
#vector io_ri.dmem_rd_data[63:0]
#watch io_ri.dmem_rd_data
#vector io_ri.pc[11:2]
#watch io_ri.pc
#vector io_ri.dma_wen[3:0]
#watch io_ri.dma_wen
#vector io_ri.final_pc[11:3]
#watch io_ri.final_pc
#vector io_ri.r_data_5[9:0]
#watch io_ri.r_data_5
#vector io_ri.imem_datain[63:0]
#watch io_ri.imem_datain
#vector io_ri.cbus_command[2:0]
#watch io_ri.cbus_command
#vector io_ri.r_data_4[0:8]
#watch io_ri.r_data_4
#vector io_ri.rbus_extend_out[7:0]
#watch io_ri.rbus_extend_out
#vector io_ri.c_ctl_i[5:0]
#watch io_ri.c_ctl_i
#vector io_ri.rac_sel_in[3:0]
#watch io_ri.rac_sel_in
#vector io_ri.rac_sel_out[3:0]
#watch io_ri.rac_sel_out
#vector io_ri.im_to_rd_data[63:0]
#watch io_ri.im_to_rd_data
#vector io_ri.r_data_3[0:8]
#watch io_ri.r_data_3
#vector io_ri.tst_c_ctl_i[5:0]
#watch io_ri.tst_c_ctl_i
#vector io_ri.rbus_control_out[7:0]
#watch io_ri.rbus_control_out
#vector io_ri.ebus_data[7:0]
#watch io_ri.ebus_data
#vector io_ri.rbus_enable_out[7:0]
#watch io_ri.rbus_enable_out

#watch  io_ri.clock
#watch io_ri.reset_l_0
#watch io_ri.rsp_0/cp0_enable 
#watch io_ri.cmd_cbus_read_enable
#watch io_ri.cmd_cbus_write_enable
#watch io_ri.cmd_dma_grant
#watch io_ri.cmd_read_grant
#watch io_ri.cbuf_ready
#watch io_ri.rsp_0/cp0_address[3] 
#watch io_ri.rsp_0/cp0_write 
#watch io_ri.cmd_busy
#watch io_ri.pipe_busy
#watch io_ri.tmem_busy
#watch io_ri.start_gclk
#watch io_ri.sp_cbus_read_enable
#watch io_ri.sp_cbus_write_enable
#watch io_ri.sp_dma_grant
#watch io_ri.sp_read_grant
#watch io_ri.rsp_0/ex_mfc0 
#watch io_ri.rsp_0/set_broke 
#watch io_ri.ri_cbus_read_enable
#watch io_ri.ri_cbus_write_enable
#watch io_ri.ri_read_grant
#watch io_ri.tst_c_ctl_en
#watch io_ri.tst_c_ctl_ld
#watch io_ri.iddq_test
#watch io_ri.mem_cbus_write_enable
#watch io_ri.rsp_0/imem_dma_cycle 
#watch io_ri.rsp_0/imem_chip_sel_l

#watch io_ri.dma_start
#watch io_ri.dma_last
#watch io_ri.cmd_dma_request
#watch io_ri.cmd_read_request
#watch io_ri.cbuf_write
#watch io_ri.flush
#watch io_ri.freeze
#watch io_ri.unfreeze
#watch io_ri.sp_dma_request
#watch io_ri.sp_read_request
#watch io_ri.mem_read_request
#watch io_ri.rsp_0/dma_imem_select 
#watch io_ri.rsp_0/dma_dm_to_rd 
#watch io_ri.rsp_0/dma_rd_to_dm 
#watch io_ri.rsp_0/halt 
#watch io_ri.rsp_0/single_step 
#watch io_ri.rsp_0/pc_in_wr_en 
#watch io_ri.sp_interrupt
#watch io_ri.dma_ready
#watch io_ri.ri_read_request
#watch io_ri.mi_dbus_read_enable
#watch io_ri.span_dbus_read_enable
#watch io_ri.mi_dbus_write_enable
#watch io_ri.pi_dbus_write_enable
#watch io_ri.si_dbus_write_enable
#watch io_ri.span_dbus_write_enable
#watch io_ri.c_ctl_en
#watch io_ri.c_ctl_ld
#watch io_ri.stop_t
#watch io_ri.stop_r
#watch io_ri.rsp_0/imem_web 
#watch io_ri.rsp_0/ex_dma_rd_to_dm 
#watch io_ri.rsp_0/ex_dma_dm_to_rd


####################################
# open trc file
####################################
# output (only) [trc]$1

####################################
# load sim file
####################################
load [sim]$1

####################################
# close trc file
####################################
# output .

####################################
# display % of nodes toggled
####################################
toggles (totals)

q
q
EOF