setup.sim
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####################################
# setup environment
####################################
radix 16
options bidirConflict
options failTestOnZ
#trace (static, tabular)
options tabularReportOnChange
trace (dynamic, tabular)
#trace (dynamic)
####################################
# rambus pullup resistors
####################################
#transistor P vss bus_enable_rac vdd
#transistor P vss bus_ctrl_rac vdd
#transistor P vss bus_data_rac[8] vdd
#transistor P vss bus_data_rac[7] vdd
#transistor P vss bus_data_rac[6] vdd
#transistor P vss bus_data_rac[5] vdd
#transistor P vss bus_data_rac[4] vdd
#transistor P vss bus_data_rac[3] vdd
#transistor P vss bus_data_rac[2] vdd
#transistor P vss bus_data_rac[1] vdd
#transistor P vss bus_data_rac[0] vdd
####################################
# display current environment
####################################
#preprocess
simparms
options
trace
modeloptions
####################################
# bus and signal aliases
####################################
vector vbus_data_pad[6:0]
vector sys_ad_pad[31:0]
vector sys_cmd_pad[4:0]
vector ad16_data_pad[15:0]
equiv sys_ad_enable_l[0] sys_ad_pad_oen
equiv sys_ad_enable_l[0] sys_cmd_pad_oen
equiv tst_ad16_enable_l[0] ad16_data_pad_oen
equiv vclk_enable_l vclk_pad_oen
equiv bus_ctrl_rac bus_ctrl_rac_i
equiv bus_ctrl_rac bus_ctrl_rac_o
equiv bus_data_rac[8] bus_data_rac_i[8]
equiv bus_data_rac[7] bus_data_rac_i[7]
equiv bus_data_rac[6] bus_data_rac_i[6]
equiv bus_data_rac[5] bus_data_rac_i[5]
equiv bus_data_rac[4] bus_data_rac_i[4]
equiv bus_data_rac[3] bus_data_rac_i[3]
equiv bus_data_rac[2] bus_data_rac_i[2]
equiv bus_data_rac[1] bus_data_rac_i[1]
equiv bus_data_rac[0] bus_data_rac_i[0]
vector bus_data_rac[8:0]
vector bus_data_rac_o[8:0] bus_data_rac[8:0]