do_sim 2.75 KB
#!/bin/csh -f
#
#  Shell script for generating tabular trace file 
#
#  Usage: do_sim <test>
#
#  12/30/94   TD
#

if ( $#argv != 1 ) then
  echo "Usage: $0 <test>"
  exit
endif

vlsishell << EOF
set echo on

####################################
# invoke qsim and load netlist
####################################
qsim
mode compassqsim
load [nls]vi

####################################
# setup environment
####################################
radix 16
options bidirConflict
options failTestOnZ
#trace (static, tabular)
options tabularReportOnChange
trace (dynamic, tabular)

####################################
# display current environment
####################################
preprocess
simparms
options
trace
modeloptions

####################################
# bus and signal aliases
####################################
vector cbus_select[1:0]
vector cbus_command[2:0]
vector dbus_data[63:0]
vector ebus_data[7:0]
vector vbus_data[6:0]
vector cbus_data[31:0]
equiv  cbus_write_enable cbus_data_oe

####################################
# list signals to be dumped in trace file
####################################
#watch clk                     
#watch vclk                    
#watch reset_l                 
#watch cbus_read_enable        
#watch cbus_write_enable       
#watch cbus_select
#watch cbus_command
#watch dma_start               
#watch dma_last                
#watch dma_grant               
#watch read_grant              
#watch dbus_data
#watch ebus_data
#watch dma_request             
#watch read_request            
#watch vbus_data
#watch vbus_sync               
#watch vbus_clock_enable_l     
#watch vi_int                  
#watch refresh_strobe          
#watch cbus_data
#watch cbus_data_oe            

#watch vclk_cell/vipipe/vigm/gamma_sync_reg.qn
#watch vclk_cell/vipipe/hlerpsync
#watch vclk_cell/vipipe/vlerp0sync
#watch vclk_cell/vipipe/divotsync
#watch vclk_cell/vipipe/filter1sync
#watch vclk_cell/vipipe/vif1/sync_eee
#watch vclk_cell/vipipe/vif2/sync_ee
#watch vclk_cell/synci

#vector span_sel_5d[1:0] vclk_cell/visync/span_sel_5d[1] vclk_cell/visync/span_sel_5d_Q1112[0]
#watch span_sel_5d
#vector span_sel_1d[1:0] vclk_cell/visync/span_sel_1d[1] vclk_cell/visync/span_sel_1d[0]
#watch span_sel_1d
#vector span_sel[1:0] vclk_cell/visync/vifsm/span_sel_reg_1_.q vclk_cell/visync/vifsm/span_sel_reg_0_.q
#watch span_sel

####################################
# open trc file
####################################
output (only) [trc]$1

####################################
# load sim file
####################################
load [sim]$1

####################################
# close trc file
####################################
output .

####################################
# display % of nodes toggled
####################################
toggles (totals)

q
q
EOF