ai.v
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/************************************************************************\
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
\************************************************************************/
// $Id: ai.v,v 1.1.1.1 2002/05/17 06:07:44 blythe Exp $
module ai(clock, reset_l,
cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
dma_start, dma_grant, read_grant, dbus_data, vbus_clock,
dma_request, read_request, abus_data, abus_word, abus_clock, ai_full,
cbus_data);
`include "ai.vh"
input clock; // system clock
input reset_l; // system reset
input cbus_read_enable; // enable cbus read mux
input cbus_write_enable; // enable cbus tristate drivers
input [CBUS_SELECT_SIZE-1:0] cbus_select; // cbus data select
input [CBUS_COMMAND_SIZE-1:0] cbus_command; // cbus data type
input dma_start; // first dbus word flag
input dma_grant; // DMA request granted
input read_grant; // read request granted
input [DBUS_DATA_SIZE-1:0] dbus_data; // DMA bus
input vbus_clock; // video transimt clock
output dma_request; // request a DMA cycle
output read_request; // request a read response cycle
output abus_data; // audio data
output abus_word; // audio high word flag
output abus_clock; // audio transmit clock
output ai_full; // ai double buffer full
inout [CBUS_DATA_SIZE-1:0] cbus_data; // IO bus
wire [DRAM_ADDRESS_SIZE-1:0] dma_address;
wire [CBUS_DATA_SIZE-1:0] reg_read_data;
wire [CBUS_DATA_SIZE-1:0] reg_write_data;
wire [AI_REG_ADDRESS_SIZE-1:0] reg_address;
wire reg_write_enable;
wire [BIT_RATE_SIZE-1:0] bit_rate_reg;
wire [DAC_RATE_SIZE-1:0] dac_rate_reg;
wire [15:0] dac_test_data;
wire [SAMPLE_WORD_SIZE-1:0] current_sample;
//
ai_dma ai_dma_0(.clock(clock), .reset_l(reset_l),
.cbus_read_enable(cbus_read_enable),
.cbus_write_enable(cbus_write_enable), .cbus_select(cbus_select),
.cbus_command(cbus_command), .dma_grant(dma_grant),
.read_grant(read_grant), .dma_address(dma_address),
.reg_read_data(reg_read_data), .read_request(read_request),
.reg_write_data(reg_write_data), .reg_address(reg_address),
.reg_write_enable(reg_write_enable), .cbus_data(cbus_data));
// instantiate DMA and register R/W controller
ai_controller ai_controller_0(.clk(clock), .reset_l(reset_l),
.dma_grant(dma_grant), .dma_start(dma_start),
.reg_write_data(reg_write_data), .reg_address(reg_address),
.reg_write_enable(reg_write_enable), .abus_word(abus_word),
.test_data(dac_test_data),
.dbus_data(dbus_data), .dma_request(dma_request),
.dma_address(dma_address), .reg_read_data(reg_read_data),
.bit_rate_reg(bit_rate_reg), .dac_rate_reg(dac_rate_reg),
.current_sample(current_sample), .interrupt_flag(ai_full));
// instantiate audio serial clock and data controller
ai_abus ai_abus_0 (.clk(vbus_clock), .reset_l(reset_l),
.bit_rate(bit_rate_reg), .dac_rate(dac_rate_reg),
.data_word(current_sample), .dac_cntr_out(dac_test_data),
.abus_data(abus_data), .abus_clk(abus_clock), .abus_wsel(abus_word));
endmodule
// eof