Makefile
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# #!smake -J3
#####################################################
# Verilog source files #
#####################################################
SRCDIR = ../src
AT_SRCS = ../src/at.v \
at_ew.edf \
at_tc.edf \
at_cc.edf \
at_bl.edf \
at_ms.edf \
at.ss
EW_SRCS = ../src/at_ew.v \
../src/at_latch_l.v \
../src/at_latch_h.v \
../src/at_latch1.v \
../src/at_latch23.v \
../src/at_latch32.v \
../src/at_latch56.v \
../src/at_latch64.v \
../src/at_ctrn.v \
../src/at_ctrb.v \
at_ew.ss
TC_SRCS = ../src/at_tc.v \
../src/at_latch_l.v \
../src/at_latch_h.v \
../src/at_latch1.v \
../src/at_latch3.v \
../src/at_latch32.v \
../src/at_latch64.v \
../src/at_ctw2.v \
../src/at_ctw3.v \
../src/at_ctr2.v \
../src/at_ctr3.v \
at_tc.ss
CC_SRCS = ../src/at_cc.v \
../src/at_latch_l.v \
../src/at_latch_h.v \
../src/at_latch32.v \
../src/at_latch56.v \
../src/at_latch64.v \
../src/at_ctw2.v \
../src/at_ctw3.v \
../src/at_ctr2.v \
../src/at_ctr3.v \
at_cc.ss
BL_SRCS = ../src/at_bl.v \
../src/at_latch_l.v \
../src/at_latch_h.v \
../src/at_latch32.v \
../src/at_latch56.v \
../src/at_latch64.v \
../src/at_ctw2.v \
../src/at_ctw3.v \
../src/at_ctr2.v \
../src/at_ctr3.v \
at_bl.ss
MS_SRCS = ../src/at_ms.v \
../src/at_latch_l.v \
../src/at_latch_h.v \
../src/at_latch56.v \
../src/at_latch64.v \
../src/at_ctw4.v \
../src/at_ctr4.v \
at_ms.ss
default : at.edf at.vsyn
at.edf : $(AT_SRCS)
at_ew.edf : $(EW_SRCS)
at_tc.edf : $(TC_SRCS)
at_cc.edf : $(CC_SRCS)
at_bl.edf : $(BL_SRCS)
at_ms.edf : $(MS_SRCS)
PRDEPTH=../../../../..
include $(PRDEPTH)/PRdefs
include $(PRDEPTH)/PRrules
LDIRT = *.log *.edf *.lint *.synlog *.vsyn