bl.ss
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module = bl
search_path = search_path + "../src" + "../../inc" + \
"../../../lib/verilog/user" + "../../syn"
/* read the verilog sources */
read -f verilog ../src/bl_add.v
read -f verilog ../src/bl_cvg2.v
read -f verilog ../src/bl_cvg3.v
read -f verilog ../src/bl_dec.v
read -f verilog ../src/bl_deltaz.v
read -f verilog ../src/bl_deltaz_quant.v
read -f verilog ../src/bl_deltaz_add15.v
read -f verilog ../src/bl_div.v
read -f verilog ../src/bl_enc.v
read -f verilog ../src/bl_exp.v
read -f verilog ../src/bl_lerp.v
read -f verilog ../src/bl_lerp_add10.v
read -f verilog ../src/bl_lerp_and.v
read -f verilog ../src/bl_lerp_fa5.v
read -f verilog ../src/bl_lerp_fa6.v
read -f verilog ../src/bl_lerp_fa7.v
read -f verilog ../src/bl_lerp_fa8.v
read -f verilog ../src/bl_lerp_fa9.v
read -f verilog ../src/bl_lerp_faso.v
read -f verilog ../src/bl_lerp_ha1.v
read -f verilog ../src/bl_lerp_ha3.v
read -f verilog ../src/bl_lerp_haso.v
read -f verilog ../src/bl_log.v
read -f verilog ../src/bl_mux8.v
read -f verilog ../src/bl_muxa.v
read -f verilog ../src/bl_muxb.v
read -f verilog ../src/bl_mxpm.v
read -f verilog ../src/bl_norm.v
read -f verilog ../src/bl_nrma.v
read -f verilog ../src/bl_nrmb.v
read -f verilog ../src/bl_zcomp_gt.v
read -f verilog ../src/bl_zcomp.v
read -f verilog ../src/bl_max.v
read -f verilog ../src/bl.v
current_design = bl
link
check_design > bl.lint
sub_modules = {bl_mux8, bl_mxpm, bl_muxa, bl_muxb, \
bl_nrma, bl_nrmb, bl_norm, bl_deltaz, \
bl_enc, bl_dec, bl_log, bl_exp, \
bl_lerp, bl_add, bl_div, bl_max, \
bl_cvg2, bl_cvg3, bl_zcomp}
foreach(module, sub_modules){
set_dont_touch module true
}
/* compile restrictions */
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* }
/* operating conditions */
set_operating_conditions NOM
set_wire_load 128000 -mode top
/* timing/area constraints */
max_area 11000
set_input_delay 2.0 all_inputs()
set_driving_cell -cell dfntnb all_inputs()
create_clock gclk -period 14.0 -waveform {0 7.0}
set_driving_cell -none {gclk}
set_dont_touch_network {gclk}
set_drive 0 {gclk}
set_arrival 0 {gclk}
set_output_delay 13.5 -clock gclk all_outputs()
set_load 0.08 all_outputs()
set_max_transition 1.1 current_design
current_design = bl
compile -map_effort high -ungroup_all
/* enforce naming restrictions for Compass tools */
change_names -rules compass_rules -hierarchy
/* standard reports & netlist */
module = bl
include "report.dc"
write -f edif -o bl.edf -hier bl
quit