Makefile 1.46 KB
#

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#  Verilog source files                             #
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SRCDIR  = ../src

CS_SRCS =       $(SRCDIR)/cs.v 	\
                csclk.edf 	\
                csgclk.edf 

GCLK_SRCS =     $(SRCDIR)/csgclk.v 	\
                csdecode.edf 		\
                csfiforptr.edf 		\
                csshuffle.edf


default : cs.vsyn

cs.vsyn: edf2vsyn.ss cs.edf
	dc_shell -f edf2vsyn.ss 

cs.edf: cs.ss $(CS_SRCS)
	dc_shell -f cs.ss | tee cs.synlog

csclk.edf: csclk.ss $(SRCDIR)/csclk.v
	dc_shell -f csclk.ss | tee csclk.synlog

csgclk.edf: csgclk.ss $(GCLK_SRCS)
	dc_shell -f csgclk.ss | tee csgclk.synlog

csdecode.edf: csdecode.ss $(SRCDIR)/csdecode.v cspartdec.edf csdatamux.edf
	dc_shell -f csdecode.ss | tee csdecode.synlog

cspartdec.edf: cspartdec.ss $(SRCDIR)/cspartdec.v
	dc_shell -f cspartdec.ss | tee cspartdec.synlog

csdatamux.edf: csdatamux.ss $(SRCDIR)/csdatamux.v
	dc_shell -f csdatamux.ss | tee csdatamux.synlog

csfiforptr.edf: csfiforptr.ss $(SRCDIR)/csfiforptr.v
	dc_shell -f csfiforptr.ss | tee csfiforptr.synlog

csshuffle.edf: csshuffle.ss $(SRCDIR)/csshuffle.v csshuftbl.edf $(SRCDIR)/csadder5b.v
	dc_shell -f csshuffle.ss | tee csshuffle.synlog

csshuftbl.edf: csshuftbl.ss $(SRCDIR)/csshuftbl.v
	dc_shell -f csshuftbl.ss | tee csshuftbl.synlog



PRDEPTH=../../../../..
include $(PRDEPTH)/PRdefs 
include $(PRDEPTH)/PRrules 
LDIRT = *.log *.edf *.lint *.synlog *.vsyn