csclk.ss
1.45 KB
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module = csclk
/* set up a new search path */
search_path = search_path + "../../inc"
/* read the verilog sources */
read -f verilog ../src/csclk.v
current_design = csclk
/* compile restrictions */
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* }
/* setup operating conditions */
set_operating_conditions NOM
set_wire_load 128000 -mode top
link
check_design > csclk.lint
/* timing/area constraints */
create_clock clk -period 14.0 -waveform {7.0 14.0}
/* inputs */
set_input_delay 4.0 -clock clk {xbus_valid}
set_input_delay 3.0 -clock clk {read_adrs[*]}
set_driving_cell -cell dfntnb {xbus_valid}
set_driving_cell -cell dfntnb {read_adrs[*]}
set_driving_cell -none {clk}
set_dont_touch_network {clk}
set_drive 0 {clk}
set_max_fanout 0.02 {reset_l}
/* outputs */
set_output_delay 5.0 -clock clk {wr_adrs[*]}
set_output_delay 7.0 -clock clk {cs_xbus_req}
set_output_delay 10.0 -clock clk {empty}
set_output_delay 10.0 -clock clk {cmd_busy}
set_output_delay 10.0 -clock clk {words_fifo[*]}
set_load 0.06 all_outputs()
set_load 0.10 {empty}
set_load 0.40 {cmd_busy}
set_load 0.60 {cs_xbus_req}
set_max_transition 0.8 current_design
max_area 100
/* compile */
compile -map_effort high -ungroup_all
report_reference
/* enforce naming restrictions for Compass tools */
change_names -rules compass_rules -hierarchy
report_constraint -all_violators
write -f edif -o csclk.edf -hier csclk
quit