ewatt.ss
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock gclk -period 15.0 -waveform {7.0 15.0}; \
set_input_delay 4.0 -clock gclk all_inputs(); \
set_output_delay 2.0 -clock gclk all_outputs(); \
set_max_delay 3.0 -to all_outputs(); \
set_load 0.2 all_outputs();"
/* read the verilog sources */
read -f verilog ../src/ewrfdelay.v
read -f verilog ../src/ew32blatch.v
read -f verilog ../src/ewrf32b18w.v
read -f verilog ../src/adder16b.v
read -f verilog ../src/ewattadder.v
read -f verilog ../src/ewshuffle.v
read -f verilog ../src/ewattseldxdy.v
read -f verilog ../src/ewattoffseti.v
read -f verilog ../src/ha.v
read -f verilog ../src/ewatt.v
set_dont_touch ewrfdelay
set_dont_touch ew32blatch
set_dont_touch ewattoffseti
set_dont_touch ha
/* set_dont_touch adder16bi */
current_design = ewatt
link
check_design > ewatt.lint
set_default_operating_conditions
create_clock gclk -period 15.0 -waveform {7.0 15.0}
set_max_transition 1.5 current_design
set_drive 0 {gclk, reset_l}
set_dont_touch_network {gclk}
set_clock_skew -uncertainty 1 gclk
fix_hold gclk
/* inputs */
set_input_delay 10.0 -clock gclk {cs_ew_data[*]}
set_input_delay 2.0 -clock gclk {dxr[*], dxg[*], dxb[*], dxa[*], dxz[*]}
set_input_delay 2.0 -clock gclk {dxs[*], dxt[*], dxw[*], dxl[*]}
set_input_delay 2.0 -clock gclk {dyr[*], dyg[*], dyb[*], dya[*], dyz[*]}
set_input_delay 2.0 -clock gclk {dys[*], dyt[*], dyw[*], dyl[*]}
set_input_delay 1.3 -clock gclk {x_frac[*]}
set_input_delay 1.3 -clock gclk {ld_x_frac}
set_input_delay 5.0 -clock gclk {wa_addr[*]}
set_input_delay 5.0 -clock gclk {wde_addr[*]}
set_input_delay 1.3 -clock gclk {ra_addr[*]}
set_input_delay 1.3 -clock gclk {rb_addr[*]}
set_input_delay 5.0 -clock gclk {wen_a}
set_input_delay 5.0 -clock gclk {wen_de}
set_input_delay 1.3 -clock gclk {add32b}
set_input_delay 1.3 -clock gclk {add_clear}
set_input_delay 5.0 -clock gclk {ld_a}
set_input_delay 1.3 -clock gclk {shuffle}
set_input_delay 1.3 -clock gclk {noshuffle}
set_input_delay 3.0 -clock gclk {ew_stall_attr}
set_input_delay 2.0 -clock gclk {left}
set_input_delay 2.0 -clock gclk {sign_dxdy}
set_input_delay 1.3 -clock gclk {seldy[*]}
set_input_delay 2.0 -clock gclk {cycle_type[*]}
set_input_delay 2.0 -clock gclk {load_cmd}
/* set input drives */
set_driving_cell -cell mx21d1 {cs_ew_data[*]}
set_driving_cell -cell dfntnh {dxr[*], dxg[*], dxb[*], dxa[*], dxz[*]}
set_driving_cell -cell dfntnh {dxs[*], dxt[*], dxw[*], dxl[*]}
set_driving_cell -cell dfntnh {dyr[*], dyg[*], dyb[*], dya[*], dyz[*]}
set_driving_cell -cell dfntnh {dys[*], dyt[*], dyw[*], dyl[*]}
set_driving_cell -cell dfntnb {x_frac[*]}
set_driving_cell -cell dfntnb {ld_x_frac}
set_driving_cell -cell mx21d1 {wa_addr[*]}
set_driving_cell -cell xo02d1 {wde_addr[*]}
set_driving_cell -cell dfntnb {ra_addr[*]}
set_driving_cell -cell dfntnb {rb_addr[*]}
set_driving_cell -cell or02d1 {wen_a}
set_driving_cell -cell or02d1 {wen_de}
set_driving_cell -cell dfntnb {add32b}
set_driving_cell -cell dfntnb {add_clear}
set_driving_cell -cell or02d1 {ld_a}
set_driving_cell -cell dfntnb {shuffle}
set_driving_cell -cell dfntnb {noshuffle}
set_driving_cell -cell dfntnh {ew_stall_attr}
set_driving_cell -cell dfntnh {left}
set_driving_cell -cell dfntnh {sign_dxdy}
set_driving_cell -cell dfntnb {seldy[*]}
set_driving_cell -cell dfntnh {cycle_type[*]}
set_driving_cell -cell dfntnh {load_cmd}
/* outputs */
set_output_delay 12.0 -clock gclk {ew_ep_d[*]}
set_load 0.08 all_outputs()
set_dont_use find(cell, "ne35hd130d/*1h")
compile -map_effort high -ungroup_all
report -reference
report_constraint -all_violators
change_names -rules compass_rules -hierarchy
write -f edif -o ewatt.edf -hier ewatt
quit