Makefile
1.13 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
#
SRCDIR = ../src
INCDIR = ../../inc
LIBDIR = ../../../lib/verilog/user
LDIRT = *.log *.edf *.lint *.synlog *.vsyn *.area *.reference \
*.clock_tree *.constraint *.summary *.timing
#############################################
# source files #
#############################################
INC_SRCS = $(INCDIR)/sp.vh \
$(INCDIR)/rcp.vh \
$(INCDIR)/reality.vh
LIB_SRCS = $(LIBDIR)/cbus_driver.v \
$(LIBDIR)/cp0_driver.v
default : all
all: io_mem_dma.vsyn io_cmd_dma.vsyn
clobber :
-rm -rf $(LDIRT)
#############################################
# synthesis dependencies #
#############################################
io_mem_dma.vsyn: io_mem_dma.edf mem_edf2vsyn.ss
dc_shell -f mem_edf2vsyn.ss
io_cmd_dma.vsyn: io_cmd_dma.edf cmd_edf2vsyn.ss
dc_shell -f cmd_edf2vsyn.ss
io_mem_dma.edf: io_mem_dma.ss $(SRCDIR)/io_mem_dma.v $(INC_SRCS) $(LIB_SRCS)
dc_shell -f io_mem_dma.ss | tee io_mem_dma.synlog
io_cmd_dma.edf: io_cmd_dma.ss $(SRCDIR)/io_cmd_dma.v $(INC_SRCS) $(LIB_SRCS)
dc_shell -f io_cmd_dma.ss | tee io_cmd_dma.synlog