io_ri.ss
5.33 KB
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "io_ri"
wire_load = 256000
standard_load = 0.01
clock = "clock"
clocks = "clock"
default_input_delay = 1.5
default_output_delay = 13.0
default_input_load = 40
default_output_load = 40
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 0.5
compile_default_critical_range = 1.0
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path + "../syn"
read -f edif module + ".edf"
include module + ".cap" > module + ".cap_errors"
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clocks -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clocks
dont_touch_network clocks
/*****************************************************************************/
/* default constraints */
/*****************************************************************************/
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 clocks
set_input_delay 0 clocks
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { *_cbus_read_enable *_cbus_write_enable }
set_load 200 * standard_load { *_dbus_read_enable *_dbus_write_enable }
set_output_delay 11.0 -clock clock { *_dbus_read_enable *_dbus_write_enable }
set_driving_cell -cell nt01d5 { cbus_data dbus_data ebus_data }
set_load 100 * standard_load { cbus_data dbus_data ebus_data }
set_input_delay 10.0 -clock clock { cbus_data dbus_data ebus_data }
set_output_delay 8.0 -clock clock { cbus_data dbus_data ebus_data }
set_driving_cell -cell ni01d5 { cbus_command }
set_load 100 * standard_load { cbus_command }
set_load 100 * standard_load { dma_start dma_last }
set_output_delay 4.5 -clock clock \
{ rbus_data_out rbus_extend_out rbus_control_out rbus_enable_out }
set_load 60 * standard_load \
{ rbus_data_out rbus_extend_out rbus_control_out rbus_enable_out }
set_input_delay 4.0 -clock clock { reset_l_0 }
set_input_delay 3.0 -clock clock { im_to_rd_data }
set_input_delay 6.0 -clock clock { dmem_rd_data }
set_input_delay 2.5 -clock clock { pc }
set_input_delay 3.5 -clock clock { rsp_0/imem_dma_cycle }
set_input_delay 5.5 -clock clock { rsp_0/imem_chip_sel_l }
set_output_delay -max 5.0 -clock clock { xbus_data }
set_output_delay -max 12.5 -clock clock { rsp_0/ex_dma_rd_to_dm }
set_output_delay -max 12.5 -clock clock { rsp_0/ex_dma_dm_to_rd }
set_output_delay -max 4.5 -clock clock { mem_write_data }
set_output_delay -max 2.0 -clock clock { imem_datain }
set_output_delay -max 10.0 -clock clock { dma_wen }
set_output_delay -max 5.0 -clock clock { cp0_data }
set_output_delay -max 11.0 -clock clock { rsp_0/dma_imem_select }
set_output_delay -max 6.5 -clock clock { final_pc }
set_output_delay -max 11.0 -clock clock { rsp_0/imem_web }
set_output_delay -max 11.0 -clock clock { c_ctl_i c_ctl_en c_ctl_ld }
/*****************************************************************************/
/* check */
/*****************************************************************************/
link
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
/* set_fix_hold all_clocks() */
compile -in_place
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "report.dc"
write -format edif -hierarchy -o module + ".edf_ipo" module
write -format db -hierarchy -o module + ".db" module
quit