#!/bin/csh -f
#

vlsishell << EOF
set echo on

#
# QTV
#
#
qtv

load [nls]ls

show simparms

clock set clk 1(8) 0(8)

set additionalCap 1.0 vu_bwe[*]
set additionalCap 1.0 ls_data_out[*]
set additionalCap 1.0 cp0_data_out[*]
set additionalCap 1.0 dmem_rd_data[*]

preprocess

set transition delay 2.5 halt
set transition delay 4.0 iddq_test

set transition delay 13.0 rd_base[*]
set transition delay 12.0 rd_offset[*]
set transition delay 8.0 rd_elem_num[*]
set transition delay 2.0 elem_num[*]
set transition delay 11.0 address[*]
set transition delay 2.0 df_ls_drive_ls_in_wb
set transition delay 2.0 df_pass_thru
set transition delay 2.0 su_ex_store
set transition delay 2.0 su_ex_load
set transition delay 2.0 vu_ex_store
set transition delay 2.0 vu_ex_load
set transition delay 2.0 ex_mtc2
set transition delay 2.0 ex_mfc2
set transition delay 2.0 ex_cfc2
set transition delay 2.0 cp0_write
set transition delay 12.0 vu_rd_ld_dec_k[*]
set transition delay 12.0 vu_rd_st_dec_k[*]
set transition delay 8.0 chip_sel
set transition delay 2.0 ex_su_byte_ls
set transition delay 2.0 ex_su_half_ls
set transition delay 2.0 ex_su_uns_ls
set transition delay 2.0 ex_dma_rd_to_dm
set transition delay 2.0 ex_dma_dm_to_rd
set transition delay 4.0 dma_wen[*]
set transition delay 1.5 dma_address[*]
set transition delay 1.5 dmem_dataout[*]
set transition delay 9.0 mem_write_data[*]
set transition delay 2.0 ex_mfc0
set transition delay 2.0 pc[*]
 
set transition delay 4.0 ls_data[*]
set transition delay 8.0 cp0_data[*]

trace critical 2;

trace delay 2;; ls_data_out[*];

trace delay 2;; dmem_rd_data[*];

exit
exit
EOF
#