#

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#  Verilog source files                             #
#####################################################
SRCDIR  = ../src

LS_SRCS =       $(SRCDIR)/ls.v \
		lsctl.edf \
		lsdp.edf

default : ls.edf 

ls.edf: ls.ss ls.con $(LS_SRCS)
	dc_shell -f ls.ss | tee ls.synlog

lsctl.edf: lsctl.ss lsctl.con $(SRCDIR)/lsctl.v ls_ex_rot_values.edf
	dc_shell -f lsctl.ss | tee lsctl.synlog

ls_ex_rot_values.edf: ls_ex_rot_values.ss $(SRCDIR)/ls_ex_rot_values.v
	dc_shell -f ls_ex_rot_values.ss | tee ls_ex_rot_values.synlog

lsdp.edf: lsdp.ss lsdp.con $(SRCDIR)/lsdp.v
	dc_shell -f lsdp.ss | tee lsdp.synlog


PRDEPTH=../../../../..
include $(PRDEPTH)/PRdefs 
include $(PRDEPTH)/PRrules 
LDIRT = *.log *.edf *.lint *.synlog *.vsyn