Makefile
1.25 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
# #! smake -J2
#####################################################
# Verilog source files #
#####################################################
SRCDIR = ../src
INCDIR = ../../inc
LIBDIR = ../../../lib/verilog/user
INC_SRCS = $(INCDIR)/ms.vh \
$(INCDIR)/rcp.vh \
$(INCDIR)/reality.vh
MS_SRCS = $(SRCDIR)/ms.v \
$(LIBDIR)/dbus_driver.v \
$(LIBDIR)/ebus_driver.v \
$(LIBDIR)/tmem_driver.v \
ms_sm.edf \
ms_sc.edf \
ms_si.edf \
ms_rp.edf \
ms_rand.edf \
ms_dma.edf \
ms_debug.edf
SI_SRCS = $(SRCDIR)/ms.v \
$(SRCDIR)/ms_latch_h.v \
$(SRCDIR)/ms_latch8n.v \
$(SRCDIR)/ms_latch10n.v \
$(SRCDIR)/ms_latch72.v \
$(SRCDIR)/ms_latch144.v
default : ms.edf ms.vsyn
ms.edf : $(MS_SRCS) $(INC_SRCS)
ms_sm.edf : $(SRCDIR)/ms_sm.v $(INC_SRCS)
ms_sc.edf : $(SRCDIR)/ms_sc.v $(INC_SRCS)
ms_si.edf : $(SI_SRCS) $(INC_SRCS)
ms_rp.edf : $(SRCDIR)/ms_rp.v $(INC_SRCS)
ms_rand.edf : $(SRCDIR)/ms_rand.v $(INC_SRCS)
ms_dma.edf : $(SRCDIR)/ms_dma.v $(LIBDIR)/cbus_driver.v $(INC_SRCS)
ms_debug.edf : $(SRCDIR)/ms_debug.v $(INC_SRCS)
PRDEPTH=../../../../..
include $(PRDEPTH)/PRdefs
include $(PRDEPTH)/PRrules
LDIRT = *.log *.edf *.lint *.synlog *.vsyn