Makefile
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#
SRCDIR = ../src
INCDIR = ../../inc
LIBDIR = ../../../lib/verilog/user
LDIRT = *.log *.edf *.lint *.synlog *.vsyn *.area *.reference \
*.clock_tree *.constraint *.summary *.timing
#############################################
# source files #
#############################################
PI_SRCS = $(SRCDIR)/pi.v \
pi_controller.edf \
pi_dma.edf
INC_FILES = $(INCDIR)/pi.vh \
$(INCDIR)/rcp.vh \
$(INCDIR)/reality.vh
default : pi.vsyn
clobber :
-rm -rf $(LDIRT)
#############################################
# synthesis dependencies #
#############################################
pi.vsyn : pi.edf edf2vsyn.ss
dc_shell -f edf2vsyn.ss
pi.edf : pi.ss $(PI_SRCS) $(INC_FILES)
dc_shell -f pi.ss | tee pi.synlog
pi_controller.edf : pi_controller.ss $(SRCDIR)/pi_controller.v $(INC_FILES)
dc_shell -f pi_controller.ss | tee pi_controller.synlog
pi_dma.edf : pi_dma.ss $(SRCDIR)/pi_dma.v $(LIBDIR)/cbus_driver.v $(INC_FILES)
dc_shell -f pi_dma.ss | tee pi_dma.synlog