#

#####################################################
#  Verilog source files                             #
#####################################################
SRCDIR  = ../src
INCDIR  = ../../inc
LIBDIR  = ../../../lib/verilog/user

INC_SRCS =      $(INCDIR)/ri.vh \
                $(INCDIR)/rcp.vh \
                $(INCDIR)/reality.vh

RI_SRCS =       $(SRCDIR)/ri.v

LIB_SRCS =      $(LIBDIR)/cbus_driver.v \
                $(LIBDIR)/dbus_driver.v \
                $(LIBDIR)/ebus_driver.v

default : ri.edf ri.vsyn

ri.edf : ri.ss $(RI_SRCS) $(LIB_SRCS) $(INC_SRCS)


PRDEPTH=../../../../..
include $(PRDEPTH)/PRdefs 
include $(PRDEPTH)/PRrules 
LDIRT = *.log *.edf *.lint *.synlog *.vsyn