rsp.qtvscr
8.02 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
#!/bin/csh -f
vlsishell << EOF
set echo on
utility netlist
read (tv) [nls]rsp
flatten (precomputer)
write [nls]rsp_f_timing
exit
exit
EOF
#
# QTV
#
#
set path= ($path /ecad/compass/v8r4.6/current/bin/)
vlsishell << EOF
set echo on
qtv
# load [nls]rsp
set loadoption piping
load [nls]rsp_f_timing
show simparms
set stable reset_l
break set data_unit.ls_data[*]
break set vu.vusl01.vudp0.vdpslctdatawb[*]
break set vu.vusl01.vudp1.vdpslctdatawb[*]
break set vu.vusl23.vudp0.vdpslctdatawb[*]
break set vu.vusl23.vudp1.vdpslctdatawb[*]
break set vu.vusl45.vudp0.vdpslctdatawb[*]
break set vu.vusl45.vudp1.vdpslctdatawb[*]
break set vu.vusl67.vudp0.vdpslctdatawb[*]
break set vu.vusl67.vudp1.vdpslctdatawb[*]
# break set data_unit.ls/lsdp/dp_to_dmem_0th_reg[*]
# break set vu.vusl01.vudp0.vdpopndtoutrf[*]
# break set vu.vusl01.vudp1.vdpopndtoutrf[*]
# break set vu.vusl23.vudp0.vdpopndtoutrf[*]
# break set vu.vusl23.vudp1.vdpopndtoutrf[*]
# break set vu.vusl45.vudp0.vdpopndtoutrf[*]
# break set vu.vusl45.vudp1.vdpopndtoutrf[*]
# break set vu.vusl67.vudp0.vdpopndtoutrf[*]
# break set vu.vusl67.vudp1.vdpopndtoutrf[*]
# break set vu.vusl01.vudp0.vdpoperands[*]
# break set vu.vusl01.vudp1.vdpoperands[*]
# break set vu.vusl23.vudp0.vdpoperands[*]
# break set vu.vusl23.vudp1.vdpoperands[*]
# break set vu.vusl45.vudp0.vdpoperands[*]
# break set vu.vusl45.vudp1.vdpoperands[*]
# break set vu.vusl67.vudp0.vdpoperands[*]
# break set vu.vusl67.vudp1.vdpoperands[*]
# break set vu.vusl01.vudp0.vdpstoredatarf[*]
# break set vu.vusl01.vudp1.vdpstoredatarf[*]
# break set vu.vusl23.vudp0.vdpstoredatarf[*]
# break set vu.vusl23.vudp1.vdpstoredatarf[*]
# break set vu.vusl45.vudp0.vdpstoredatarf[*]
# break set vu.vusl45.vudp1.vdpstoredatarf[*]
# break set vu.vusl67.vudp0.vdpstoredatarf[*]
# break set vu.vusl67.vudp1.vdpstoredatarf[*]
# break set su.sudp.suLoadEn.z[*]
trace critical 1
trace critical 100; rsp_critical_dmem0th
##########
break remove data_unit.ls_data[*]
break remove vu.vusl01.vudp0.vdpslctdatawb[*]
break remove vu.vusl01.vudp1.vdpslctdatawb[*]
break remove vu.vusl23.vudp0.vdpslctdatawb[*]
break remove vu.vusl23.vudp1.vdpslctdatawb[*]
break remove vu.vusl45.vudp0.vdpslctdatawb[*]
break remove vu.vusl45.vudp1.vdpslctdatawb[*]
break remove vu.vusl67.vudp0.vdpslctdatawb[*]
break remove vu.vusl67.vudp1.vdpslctdatawb[*]
break set data_unit.ls/lsdp/dp_to_dmem_0th_reg[*]
break set vu.vusl01.vudp0.vdpopndtoutrf[*]
break set vu.vusl01.vudp1.vdpopndtoutrf[*]
break set vu.vusl23.vudp0.vdpopndtoutrf[*]
break set vu.vusl23.vudp1.vdpopndtoutrf[*]
break set vu.vusl45.vudp0.vdpopndtoutrf[*]
break set vu.vusl45.vudp1.vdpopndtoutrf[*]
break set vu.vusl67.vudp0.vdpopndtoutrf[*]
break set vu.vusl67.vudp1.vdpopndtoutrf[*]
break set vu.vusl01.vudp0.vdpoperands[*]
break set vu.vusl01.vudp1.vdpoperands[*]
break set vu.vusl23.vudp0.vdpoperands[*]
break set vu.vusl23.vudp1.vdpoperands[*]
break set vu.vusl45.vudp0.vdpoperands[*]
break set vu.vusl45.vudp1.vdpoperands[*]
break set vu.vusl67.vudp0.vdpoperands[*]
break set vu.vusl67.vudp1.vdpoperands[*]
break set vu.vusl01.vudp0.vdpstoredatarf[*]
break set vu.vusl01.vudp1.vdpstoredatarf[*]
break set vu.vusl23.vudp0.vdpstoredatarf[*]
break set vu.vusl23.vudp1.vdpstoredatarf[*]
break set vu.vusl45.vudp0.vdpstoredatarf[*]
break set vu.vusl45.vudp1.vdpstoredatarf[*]
break set vu.vusl67.vudp0.vdpstoredatarf[*]
break set vu.vusl67.vudp1.vdpstoredatarf[*]
# break set su.sudp.suLoadEn.z[*]
trace critical 1
trace critical 100; rsp_critical_lsdata
trace delay 1; ex_su_byte_ls; data_unit.ls/lsdp/dp_to_dmem_3rd[119];
trace delay 1; data_unit.ls/wb_pass_thru; data_unit.ls/lsdp/dp_to_dmem_3rd[109];
trace delay 1; data_unit.ls/wb_pass_thru; data_unit.ls/lsdp/dp_to_dmem_3rd[*];
#######
clock set clk 1(10.0) 0(10.0)
clock show
set transition delay 3 reset_l
set transition delay 5 iddq_test
set transition delay 10 frozen
set transition delay 3 sp_cbus_read_enable
set transition delay 3 sp_cbus_write_enable
set transition delay 3 mem_cbus_write_enable
set transition delay 3 cmd_cbus_read_enable
set transition delay 3 cmd_cbus_write_enable
set transition delay 3 cbus_select[*]
set transition delay 3 cbus_command[*]
set transition delay 3 dma_start
set transition delay 3 dma_last
set transition delay 3 sp_dma_grant
set transition delay 3 sp_read_grant
set transition delay 3 cmd_dma_grant
set transition delay 3 cmd_read_grant
set transition delay 3 sp_dbus_read_enable
set transition delay 3 sp_dbus_write_enable
set transition delay 3 cbuf_ready
set transition delay 3 cmd_busy
set transition delay 3 pipe_busy
set transition delay 3 tmem_busy
set transition delay 12 cbus_data[*]
set transition delay 12 dbus_data[*]
break remove data_unit.ls/lsdp/dp_to_dmem_0th_reg[*]
break set data_unit.ls_data[*]
# break set su.sudp.suLoadEn.z[*]
break remove vt_decoded_a[*]
break remove vt_decoded_b[*]
break remove vu_elem[*]
break remove vu_func[*]
trace critical 1
break remove data_unit.ls_data[*]
break set data_unit.ls/lsdp/dp_to_dmem_0th_reg[*]
# break set su.sudp.suLoadEn.z[*]
trace critical 1
break set vdpoperandtrf[*]
break set vdpoperands[*]
break set vdpstoredatarf[*]
trace critical 1
break set data_unit.ls_data[*]
break remove data_unit.ls/lsdp/dp_to_dmem_0th_reg[*]
# break set su.sudp.suLoadEn.z[*]
trace critical 1
setuphold check rsp.violators
skew
# set cap 0.5 .output
# set cap 0.5 cbus_data[*]
# set cap 0.5 dbus_data[*]
# The following are top level wires of the rsp therefore we will set higher
# capacitance on these nodes.
#
# set cap 0.5 rd_inst[*]
# set cap 0.5 branch_or_addr[*]
# set cap 0.5 final_pc[*]
# set cap 0.5 pc[*]
# set cap 0.5 set_broke
# set cap 0.5 imem_dma_cycle
# set cap 0.5 imem_web
# set cap 0.5 rd_base[*]
# set cap 0.5 rd_offset[*]
# set cap 0.5 rd_elem_num[*]
# set cap 0.5 elem_num[*]
# set cap 0.5 vu_ex_load
# set cap 0.5 vu_ex_store
# set cap 0.5 su_ex_load
# set cap 0.5 su_ex_store
# set cap 0.5 ex_mfc2
# set cap 0.5 ex_mtc2
# set cap 0.5 ex_cfc2
# set cap 0.5 ex_mfc0
# set cap 0.5 vu_rd_ld_dec_k[*]
# set cap 0.5 vu_rd_st_dec_k[*]
# set cap 0.5 vu_bwe[*]
# set cap 0.5 ls_data[*]
# set cap 0.5 df_ls_drive_ls_in_wb
# set cap 0.5 df_pass_thru
# set cap 0.5 chip_sel
# set cap 0.5 dmem_rd_data[*]
# set cap 0.5 mem_write_data[*]
# set cap 0.5 ex_su_byte_ls
# set cap 0.5 ex_su_half_ls
# set cap 0.5 ex_su_uns_ls
# set cap 0.5 imem_chip_sel_l
# set cap 0.5 imem_csb
# set cap 0.5 vu_comp_k
# set cap 0.5 vu_func[*]
# set cap 0.5 ex_ctc2_vc0
# set cap 0.5 ex_ctc2_vc1
# set cap 0.5 ex_ctc2_vc2
# set cap 0.5 vu_rd_store_type_k
# set cap 0.5 vu_rd_storecfc2_k
# set cap 0.5 vs_eq_one
# set cap 0.5 vu_elem[*]
# set cap 0.5 vu_ld_addr[*]
# set cap 0.5 vu_st_addr[*]
# set cap 0.5 vu_st_xpose_addr[*]
# set cap 0.5 vs[*]
# set cap 0.5 vt_decode_a[*]
# set cap 0.5 vt_decode_b[*]
# set cap 0.5 acc_wr_reg[*]
# set cap 0.5 acc_wr_en
# set cap 0.5 xpose
# set cap 0.5 rd_cfvc0_k
# set cap 0.5 rd_cfvc1_k
# set cap 0.5 rd_cfvc2_k
# set cap 0.5 halt
# set cap 0.5 single_step
# set cap 0.5 pc_data_in[*]
# set cap 0.5 pc_in_wr_en
# set cap 0.5 cp0_data[*]
# set cap 0.5 cp0_address[*]
# set cap 0.5 cp0_write
# set cap 0.5 cp0_enable
# set cap 0.5 dma_imem_select
# set cap 0.5 dma_wen[*]
# set cap 0.5 dma_address[*]
# set cap 0.5 ex_dma_rd_to_dm
# set cap 0.5 ex_dma_dm_to_rd
# set cap 0.5 dma_rd_to_dm
# set cap 0.5 dma_dm_to_rd
# set cap 0.5 dma_mask[*]
# set cap 0.5 io_read_select
# set cap 0.5 io_write_select
# set cap 0.5 mem_load
# set cap 0.5 io_load
# set cap 0.5 xbus_dmem_select
# set cap 0.5 cmd_read
# set cap 0.5 cmd_ready
# set cap 0.5 cmd_address[*]
# set cap 0.5 imem_datain[*]
# set cap 0.5 bist_done
# set cap 0.5 bist_fail[*]
# set cap 0.5 bist_go
# set cap 0.5 bist_check
break set vu.vusl45.vudp0.vdpslctdatawb[*]
break set vu.vusl45.vudp1.vdpslctdatawb[*]
break set vu.vusl67.vudp0.vdpslctdatawb[*]
break set vu.vusl67.vudp1.vdpslctdatawb[*]
# break set data_unit.ls_data[*]
break set data_unit.ls/lsdp/dp_to_dmem_0th_reg[*]
# break set su.sudp.suLoadEn.z[*]
trace critical 100
##########
break remove data_unit.ls_data[*]
break set data_unit.ls/lsdp/dp_to_dmem_0th_reg[*]
# break set su.sudp.suLoadEn.z[*]
exit
exit
EOF
#