rspbusses.qtvscr
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#!/bin/csh -f
#
set path= ($path /ecad/compass/v8r4.6/current/bin/)
vlsishell << EOF
set echo on
#
# QTV
#
#
qtv
load [nls]rspbusses
show simparms
set capacitance 2.0 cbus_data[*]
set capacitance 2.0 dbus_data[*]
set capacitance 2.0 xbus_data[*]
set capacitance 1.4 ex_dma_rd_to_dm
set capacitance 1.4 ex_dma_dm_to_rd
set capacitance 1.5 mem_write_data[*]
set capacitance 1.5 imem_datain[*]
set capacitance 1.2 dma_wen[*]
set capacitance 1.4 final_pc[*]
set capacitance 1.8 imem_web
set capacitance 2.0 bist_done
set capacitance 0.2 bist_fail[*]
clock set clk 1(8) 0(8)
set stable reset_l
preprocess
set transition delay 8.0 reset_l
set transition delay 4.0 iddq_test
set transition delay 1.5 cbus_write_enable
set transition delay 1.5 dbus_read_enable
set transition delay 1.5 dbus_write_enable
set transition delay 5.0 io_load
set transition delay 1.5 io_read_select
set transition delay 1.5 io_write_select
set transition delay 1.5 dma_imem_select
set transition delay 1.5 xbus_dmem_select
set transition delay 1.5 dma_dm_to_rd
set transition delay 1.5 dma_rd_to_dm
set transition delay 1.5 dma_address[*]
set transition delay 1.5 dma_mask[*]
set transition delay 1.5 mem_load
set transition delay 3.0 im_to_rd_data[*]
set transition delay 6.0 dmem_rd_data[*]
set transition delay 2.5 pc[*]
set transition delay 3.5 imem_dma_cycle
set transition delay 5.5 imem_chip_sel_l
set transition delay 1.5 bist_go
set transition delay 1.5 bist_check
set transition delay 2.0 cbus_data[*]
set transition delay 2.0 dbus_data[*]
trace delay ;; cbus_data[*]
trace delay ;; dbus_data[*]
trace delay ;; xbus_data[*]
trace delay ;; ex_dma_rd_to_dm
trace delay ;; ex_dma_dm_to_rd
trace delay ;; mem_write_data[*]
trace delay ;; imem_datain[*]
trace delay ;; dma_wen[*]
trace delay ;; final_pc[*]
trace delay ;; imem_web
trace delay ;; bist_done
trace delay ;; bist_fail[*]
trace critical 10
exit
exit
EOF
#