set_input_delay 4.0 -clock clk {reset_l};
set_input_delay 1.5 -clock clk {cbus_write_enable};	/* from Jeff */
set_input_delay 1.5 -clock clk {dbus_read_enable}; 	/* from Jeff */
set_input_delay 1.5 -clock clk {dbus_write_enable};	/* from Jeff */ 
set_input_delay 5.0 -clock clk {io_load}; 		/* from Jeff */
set_input_delay 1.5 -clock clk {io_read_select};	/* from Jeff */
set_input_delay 1.5 -clock clk {io_write_select};	/* from Jeff */
set_input_delay 1.5 -clock clk {dma_imem_select};	/* from Jeff */ 
set_input_delay 1.5 -clock clk {xbus_dmem_select};	/* from Jeff */
set_input_delay 1.5 -clock clk {dma_dm_to_rd};	 	/* from Jeff */
set_input_delay 1.5 -clock clk {dma_rd_to_dm};		/* from Jeff */ 
set_input_delay 1.5 -clock clk {dma_address};		/* from Jeff */
set_input_delay 1.5 -clock clk {dma_mask}; 		/* from Jeff */ 
set_input_delay 1.5 -clock clk {mem_load}; 		/* from Jeff */ 

set_input_delay 3.0 -clock clk {im_to_rd_data}; 
set_input_delay 6.0 -clock clk {dmem_rd_data};
set_input_delay 2.5 -clock clk {pc};
set_input_delay 3.5 -clock clk {imem_dma_cycle};
set_input_delay 5.5 -clock clk {imem_chip_sel_l};

set_input_delay 1.5 -clock clk {bist_go}; 		/* from Jeff */
set_input_delay 1.5 -clock clk {bist_check}; 		/* from Jeff */

set_input_delay 2.0 -clock clk {cbus_data};		/* from Jeff */
set_input_delay 2.0 -clock clk {dbus_data}; 		/* from Jeff */

set_output_delay -max 4.0 -clock clk {cbus_data};	/* from Jeff */
set_output_delay -max 4.0 -clock clk {dbus_data};	/* from Jeff */ 

set_output_delay -max 5.3 -clock clk {xbus_data};	/* Mike: @10.5 */
set_output_delay -max 11.4 -clock clk {ex_dma_rd_to_dm};
set_output_delay -max 11.4 -clock clk {ex_dma_dm_to_rd};
set_output_delay -max 4.5 -clock clk {mem_write_data};
set_output_delay -max 2.0 -clock clk {imem_datain};
set_output_delay -max 10.0 -clock clk {dma_wen};

set_output_delay -max 7.0 -clock clk {final_pc};
set_output_delay -max 10.0 -clock clk {imem_web};
set_output_delay -max 7.0 -clock clk {imem_csb};
set_output_delay -max 10.8 -clock clk {bist_done};	/* from Jeff */
set_output_delay -max 10.8 -clock clk {bist_fail};	/* from Jeff */
set_output_delay -max 0.5 -clock clk {debug_pc};

set_max_fanout 0.2 {xbus_dmem_select}
set_driving_cell -cell ni01d5 {xbus_dmem_select}
set_driving_cell -cell ni01d5 {cbus_write_enable};	/* from Jeff */
set_driving_cell -cell ni01d5 {dbus_read_enable}; 	/* from Jeff */
set_driving_cell -cell ni01d5 {dbus_write_enable};	/* from Jeff */ 
set_driving_cell -cell nt01d4 {cbus_data, dbus_data};	/* from Jeff */

set_load 2.0 {cbus_data, dbus_data};			/* from Jeff */
set_load 2.0 {xbus_data};
set_load 1.4 {ex_dma_rd_to_dm};
set_load 1.4 {ex_dma_dm_to_rd};
set_load 1.5 {mem_write_data};

set_load 1.5 {imem_datain};
set_load 1.2 {dma_wen};

set_load 1.4 {final_pc};
set_load 1.8 {imem_web};
set_load 2.0 {bist_done};
set_load 0.2 {bist_fail};

set_max_fanout 0.02 {reset_l}