/* setup aliases */

alias set_default_operating_conditions \
	"set_operating_conditions NOM -library rcp.db; \
	set_wire_load 256000 -mode top;"
alias set_default_timing_constraints \
	"create_clock clk -period 14.0 -waveform {0 8.0}; \
	set_input_delay 4.0 -clock clk all_inputs(); \
	set_output_delay -max 2.0 -clock clk all_outputs(); \
	max_delay 14.0 -to all_outputs(); \
	set_load 0.2 all_outputs();"

/* setup the search path for includes */
search_path = search_path + "../../inc" 

/* read the verilog sources */

read -f verilog ../src/rspbusses.v
read -f verilog ../src/ram_bist_imem.v
read -f verilog ../../../lib/verilog/user/asdff.v
read -f verilog ../../../lib/verilog/user/asdffen.v
read -f verilog ../../../lib/verilog/user/cbus_driver.v
read -f verilog ../../../lib/verilog/user/dbus_driver.v

current_design = rspbusses

set_dont_touch { ne35hd130d/nt01d* }

set_default_operating_conditions
set_default_timing_constraints
set_max_transition 2.0 current_design;

include rspbusses.con
link 

check_design > rspbusses.lint

compile -map_effort high -ungroup_all

report -reference
report_constraint -all_violators
report_timing -path full -delay max -max_paths 50

write -f edif -o rspbusses.edf -hier rspbusses
write -f verilog -o rspbusses.vsyn -hier rspbusses

quit