si.ss
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module = si
/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock clk -period 16.0 -waveform {0 8.0}; \
set_input_delay 4.0 -clock clk all_inputs(); \
set_output_delay 2.0 -clock clk all_outputs(); \
max_delay 12.0 -to all_outputs(); \
set_load 0.2 all_outputs();"
standard_load = 0.01
/* set up a new search path */
search_path = search_path + "../../inc" + "../../syn"
/* read the verilog sources */
read -f verilog ../src/si.v
read -f verilog ../src/si_dma.v
read -f verilog ../src/si_control.v
read -f verilog ../src/si_pchclk.v
read -f verilog ../src/si_pif_if.v
read -f verilog ../../../lib/verilog/user/dbus_driver.v
read -f verilog ../../../lib/verilog/user/cbus_driver.v
current_design = si_pif_if
set_dont_touch si_pif_if
set_driving_cell -cell dfntnb pch_reg_msb
set_driving_cell -cell dfntnb pch_cmd_valid
set_driving_cell -cell pc3d01 pch_rsp_in
current_design = si_pchclk
set_register_type -exact -flip_flop dfntnh { find (cell,"pchclk_reg") }
current_design = si
set_default_operating_conditions
set_default_timing_constraints
set_max_transition 1.5 current_design
set_dont_use {ne35hd130d/mbnfnq ne35hd130d/mbnfnr}
set_dont_use find(cell, "ne35hd130d/*1h")
set_drive 0 { clk }
set_arrival 0 clk
set_dont_touch_network { clk }
set_max_fanout 0.02 { reset_l }
set_input_delay 8 -clock clk reset_l
set_dont_touch { ne35hd130d/nt01d* }
set_driving_cell -cell ni01d5 { *_read_enable *_write_enable }
set_driving_cell -cell nt01d4 { cbus_data dbus_data}
set_load 200 * standard_load { cbus_data dbus_data}
set_input_delay 2.0 -clock clk { cbus_data dbus_data }
set_output_delay 4.0 -clock clk { cbus_data dbus_data }
set_driving_cell -cell ni01d5 { dma_start }
set_load 100 * standard_load { dma_start }
set_max_fanout 10 * standard_load { dma_start }
set_driving_cell -cell ni01d5 { cbus_command cbus_select }
set_load 100 * standard_load { cbus_command cbus_select }
set_max_fanout 10 * standard_load { cbus_command cbus_select }
max_area 0
link
check_design > si.lint
compile -map_effort high -ungroup_all
report -reference
report_constraint -all_violators
report_clock
include "report.dc"
write -f edif -o si.edf -hier si
write -f db -o si.db -hier si
quit