ststwl.ss
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock gclk -period 14.0 -waveform {0 8.0}; \
set_input_delay 2.0 -clock gclk all_inputs(); \
set_output_delay 12.0 -clock gclk all_outputs(); \
set_max_transition 1.2 current_design; \
set_load 0.06 all_outputs();"
/* read the verilog sources */
read -f verilog ../src/adder27b.v
read -f verilog ../src/ststwl.v
current_design = ststwl
link
check_design > ststwl.lint
set_default_operating_conditions
set_default_timing_constraints
set_driving_cell -cell dfntnb {att_data_in[*]}
set_driving_cell -cell dfntnb {dx[*]}
set_driving_cell -cell dfntnb {left_major}
set_driving_cell -cell dfntnb {load, ncyc}
set_load 0.30 all_outputs()
set_output_delay 13.0 -clock gclk all_outputs()
compile -map_effort high -ungroup_all
change_names -rules compass_rules -hierarchy
report -reference
report_constraint -all_violators
write -f edif -o ststwl.edf -hier ststwl
quit