#!/bin/csh -f
#

rm sudp.nls*

set path= ($path /ecad/compass/v8r4.6/current/bin/) 
vlsishell << EOF
set echo on
#
# Switch in the sudp timing netlist
#

util netlist
read [nls]sudp_l
write (hier) [nls]sudp
quit

#
# QTV
#
#
qtv

load [nls]su
show simparms

set capacitance .7 chip_sel

set capacitance .7 rd_base[*]
set capacitance .7 rd_offset[*]
set capacitance .7 rd_elem_num[*]

set capacitance .7 su_ex_store
set capacitance .7 su_ex_load
set capacitance .7 vu_ex_store
set capacitance .7 vu_ex_load
set capacitance .7 ex_mfc2
set capacitance .7 ex_mtc2
set capacitance .7 ex_cfc2
set capacitance .7 ex_mfc0
set capacitance .7 ex_su_byte_ls
set capacitance .7 ex_su_half_ls
set capacitance .7 ex_su_uns_ls
set capacitance .7 df_ls_drive_ls_in_wb
set capacitance .7 df_pass_thru

set capacitance .7 imem_chip_sel_l
set capacitance .7 imem_dma_cycle
set capacitance .7 pc[*]

set capacitance .7 branch_or_addr[*]
set capacitance .7 elem_num[*]
set capacitance .7 set_broke
set capacitance .7 vu_rd_ld_dec_k[*]
set capacitance .7 vu_rd_st_dec_k[*]

set capacitance .7 ls_data[*]

set capacitance 1.7 vu_comp_k
set capacitance 1.7 vu_func
set capacitance 1.7 ex_ctc2_vc0
set capacitance 1.7 ex_ctc2_vc1
set capacitance 1.7 ex_ctc2_vc2
set capacitance 1.7 vu_rd_store_type_k
set capacitance 1.7 vu_rd_storecfc2_k
set capacitance 1.7 vs_eq_one
set capacitance 1.7 vu_elem[*]
set capacitance 1.7 vu_ld_addr[*]
set capacitance 1.7 vu_st_addr[*]
set capacitance 1.7 vu_st_xpose_addr[*]
set capacitance 1.7 vs[*] 
set capacitance 1.7 vt_decoded_a[*] 
set capacitance 1.7 vt_decoded_b[*] 
set capacitance 1.7 acc_wr_reg[*] 
set capacitance 1.7 acc_wr_en
set capacitance 1.7 xpose
set capacitance 1.7 rd_cfvc0_k
set capacitance 1.7 rd_cfvc1_k
set capacitance 1.7 rd_cfvc2_k

set capacitance .7 cp0_address[*] 
set capacitance .7 cp0_write 
set capacitance .7 cp0_enable 

clock set clk 1(8) 0(8)
set stable reset_l

preprocess

set transition delay 8.0 reset_l
set transition delay 2.5 halt
set transition delay 2.5 single_step
set transition delay 2.5 pc_in_wr_en
set transition delay 2.5 pc_data_in[*]
set transition delay 2.5 dma_dm_to_rd
set transition delay 2.5 dma_rd_to_dm
set transition delay 2.5 dma_imem_select
set transition delay 1.5 rd_inst[*]
set transition delay 14.5 ls_data[*]

break set sudp.suLoadEn.Z[*]

trace delay ;; sudp.suLoadEn.Z[*]





trace delay ;; chip_sel





trace delay ;; rd_base[*]





trace delay ;; rd_offset[*]





trace delay ;; rd_elem_num[*]





trace delay ;; su_ex_store





trace delay ;; su_ex_load





trace delay ;; vu_ex_store





trace delay ;; vu_ex_load





trace delay ;; ex_mfc2





trace delay ;; ex_mtc2





trace delay ;; ex_cfc2





trace delay ;; ex_mfc0





trace delay ;; ex_su_byte_ls





trace delay ;; ex_su_half_ls





trace delay ;; ex_su_uns_ls





trace delay ;; df_ls_drive_ls_in_wb





trace delay ;; df_pass_thru





trace delay ;; imem_chip_sel_l 





trace delay ;; imem_dma_cycle 





trace delay ;; su_nop_debug 





trace delay ;; vu_nop_debug 





trace delay ;; pc[*]





trace delay ;; branch_or_addr[*]





trace delay ;; elem_num[*]





trace delay ;; set_broke





trace delay ;; vu_rd_ld_dec_k[*]





trace delay ;; vu_rd_st_dec_k[*]





trace delay ;; break_inst_debug





trace delay ;; ls_data[*]





trace delay ;; vu_comp_k





trace delay ;; vu_func[*]





trace delay ;; ex_ctc2_vc0





trace delay ;; ex_ctc2_vc1





trace delay ;; ex_ctc2_vc2





trace delay ;; vu_rd_store_type_k





trace delay ;; vu_rd_storecfc2_k





trace delay ;; vs_eq_one





trace delay ;; vu_elem[*]





trace delay ;; vu_ld_addr[*]





trace delay ;; vu_st_addr[*]





trace delay ;; vu_st_xpose_addr[*]





trace delay ;; vs[*]





trace delay ;; vt_decoded_a[*]





trace delay ;; vt_decoded_b[*]





trace delay ;; acc_wr_reg[*]





trace delay ;; acc_wr_en 





trace delay ;; xpose 





trace delay ;; rd_cfvc0_k





trace delay ;; rd_cfvc1_k





trace delay ;; rd_cfvc2_k





trace delay ;; cp0_address[*]





trace delay ;; cp0_write 





trace delay ;; cp0_enable





trace critical 20





















































































































exit
exit
EOF
#