su.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: su.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $
// su.v: RSP scalar unit datapath and control
`timescale 1ns / 10ps
module su (clk, reset_l,
halt, single_step, pc_in_wr_en, pc_data_in,
dma_dm_to_rd, dma_rd_to_dm, dma_imem_select, rd_inst,
rd_base, rd_offset, rd_elem_num,
chip_sel, su_ex_store, su_ex_load, vu_ex_store, vu_ex_load,
ex_mfc2, ex_mtc2, ex_cfc2, ex_mfc0,
ex_su_byte_ls, ex_su_half_ls, ex_su_uns_ls,
df_ls_drive_ls_in_wb, df_pass_thru,
imem_chip_sel_l, imem_dma_cycle,
su_nop_debug, vu_nop_debug, pc,
branch_or_addr, elem_num, set_broke, vu_rd_ld_dec_k, vu_rd_st_dec_k,
break_inst_debug,
ls_data,
vu_comp_k, vu_func, ex_ctc2_vc0, ex_ctc2_vc1, ex_ctc2_vc2,
vu_rd_store_type_k, vu_rd_storecfc2_k, vs_eq_one, vu_elem,
vu_ld_addr, vu_st_addr, vu_st_xpose_addr,
vs, vt_decoded_a, vt_decoded_b, acc_wr_reg, acc_wr_en, xpose,
rd_cfvc0_k, rd_cfvc1_k, rd_cfvc2_k,
cp0_address, cp0_write, cp0_enable);
input clk;
input reset_l;
input halt;
input single_step;
input pc_in_wr_en;
input [11:2] pc_data_in;
input dma_dm_to_rd;
input dma_rd_to_dm;
input dma_imem_select;
input [63:0] rd_inst;
output chip_sel;
output [3:0] rd_base;
output [3:0] rd_offset;
output [3:0] rd_elem_num;
output su_ex_store;
output su_ex_load;
output vu_ex_store;
output vu_ex_load;
output ex_mfc2;
output ex_mtc2;
output ex_cfc2;
output ex_mfc0;
output ex_su_byte_ls;
output ex_su_half_ls;
output ex_su_uns_ls;
output df_ls_drive_ls_in_wb;
output df_pass_thru;
output imem_chip_sel_l; // pre-IF stage to IMem
output imem_dma_cycle; // IF stage to BIST
output su_nop_debug; // RD stage to nowhere
output vu_nop_debug; // RD stage to nowhere
output [11:2] pc; // to IO land
output [11:0] branch_or_addr;
output [3:0] elem_num;
output set_broke;
output [11:0] vu_rd_ld_dec_k; // RD stage
output [11:0] vu_rd_st_dec_k; // RD stage
output break_inst_debug;
inout [31:0] ls_data;
// Controls for VU
output vu_comp_k;
output [5:0] vu_func;
output ex_ctc2_vc0;
output ex_ctc2_vc1;
output ex_ctc2_vc2;
output vu_rd_store_type_k;
output vu_rd_storecfc2_k;
output vs_eq_one;
output [3:0] vu_elem;
output [4:0] vu_ld_addr;
output [4:0] vu_st_addr;
output [4:0] vu_st_xpose_addr;
output [4:0] vs; // RD: reg num for vs read
output [31:0] vt_decoded_a; // RD: decoded reg num for vt read
output [31:0] vt_decoded_b; // RD: decoded reg num for vt read
output [4:0] acc_wr_reg; // ACC: reg num for datapath writeback
output acc_wr_en; // ACC: write en for dp results
output xpose; // RD: st xpose or ACC: ld xpose
output rd_cfvc0_k;
output rd_cfvc1_k;
output rd_cfvc2_k;
// DMA-related IO
output [3:0] cp0_address; // EX
output cp0_write; // CTC0, EX
output cp0_enable; // CFC0, EX
// RD stage
wire [31:0] su_inst;
wire su_inst_6;
wire su_inst_15;
wire [31:0] surfile_ra_t; // decoded ra addr
wire [31:0] surfile_ra_f; // decoded ra addr, complement
wire [31:0] surfile_rb_t; // decoded rb addr
wire [31:0] surfile_rb_f; // decoded rb addr, complement
wire [4:0] surdamux;
wire [5:0] surdbmux;
wire [3:0] suimmmux; // sext or zext immediate
wire [1:0] suimmlsmux;
wire [4:0] suvulsoffsetmux; // vu l/s offset generation
wire [4:0] sushvamt;
wire [11:0] branch_or_addr_unbuf;
wire [23:0] link_pc_delay_pc; // EX stage to LS
wire sudrivels;
wire [1:0] sualuamux; // EX stage
wire [1:0] sualubmux;
wire [3:0] sushamux;
wire [2:0] sushbmux;
wire suslten;
wire susltlt;
wire sualuen;
wire [4:0] sualu;
wire sualu_cin;
wire sualu_cout_l; // active low
wire sualu_ovr;
wire sualumsb;
wire sushen;
wire [31:0] shiftamt;
wire sushift_s;
wire suonesdet_z;
wire suexasign;
wire suexbsign;
// WB stage
wire [31:0] surfile_w_t; // decoded write en
wire [31:0] surfile_w_f; // decoded write en, complement
wire suwben; // enable wb_data into RFile
wire su_mem_wen; // enable load data into RFile
wire [4:0] rd_pre_vt; // vt generation
wire [1:0] vt_sel; // vt generation
sudp sudp (
.sudwff_cp (clk),
.suedff_cp (clk),
.sualuamux (sualuamux[1:0]),
.sualubmux (sualubmux[1:0]),
.sushamux (sushamux),
.sushbmux (sushbmux),
.suslten (suslten),
.sushvamt (sushvamt),
.sushift_s (sushift_s),
.surfile_wh (surfile_w_t[31:16]),
.surfile_wl (surfile_w_t[15:0]),
.surfile_whb (surfile_w_f[31:16]),
.surfile_wlb (surfile_w_f[15:0]),
.sureinstff_cp (clk),
.surebff_cp (clk),
.sureaff_cp (clk),
.surdbmux (surdbmux),
.suonesdet_z (suonesdet_z),
.surdamux (surdamux),
.sualu_ovr (sualu_ovr),
.sualu_cout (sualu_cout_l),
.sualu_cin (sualu_cin),
.sualumsb (sualumsb),
.sualu (sualu[4:0]),
.surfile_rbh (surfile_rb_t[31:16]),
.surfile_rbl (surfile_rb_t[15:0]),
.surfile_rbhb (surfile_rb_f[31:16]),
.surfile_rblb (surfile_rb_f[15:0]),
.surfile_rah (surfile_ra_t[31:16]),
.surfile_ral (surfile_ra_t[15:0]),
.surfile_rahb (surfile_ra_f[31:16]),
.surfile_ralb (surfile_ra_f[15:0]),
.suimmmux (suimmmux),
.suimmlsmux (suimmlsmux),
.suvulsoffsetmux (suvulsoffsetmux),
.suexasign (suexasign),
.suexbsign (suexbsign),
.sualuen (sualuen),
.susltlt (susltlt),
.sushen (sushen),
.suwben (suwben),
.suloaden (su_mem_wen),
.shiftamt (shiftamt[31:0]),
.inst_data ({su_inst_15, su_inst[14:7],
su_inst_6, su_inst[5:0]}),
.branch_or_addr (branch_or_addr_unbuf[11:0]),
.link_pc_delay_pc (link_pc_delay_pc),
.sudrivels (sudrivels),
.ls_data (ls_data[31:0])
);
suctl suctl (
.clk (clk),
.reset_l (reset_l),
.halt (halt),
.single_step (single_step),
.pc_in_wr_en (pc_in_wr_en),
.pc_data_in (pc_data_in),
.dma_dm_to_rd (dma_dm_to_rd),
.dma_rd_to_dm (dma_rd_to_dm),
.dma_imem_select (dma_imem_select),
.br_addr (branch_or_addr_unbuf[11:2]),
.rd_inst (rd_inst),
.rd_base (rd_base),
.rd_offset (rd_offset),
.rd_elem_num (rd_elem_num),
.sushvamt (sushvamt),
.sualu_cout_l (sualu_cout_l),
.sualu_ovr (sualu_ovr),
.sualumsb (sualumsb),
.suexasign (suexasign),
.suexbsign (suexbsign),
.suonesdet_z (suonesdet_z),
.su_inst (su_inst),
.surfile_ra_t (surfile_ra_t),
.surfile_ra_f (surfile_ra_f),
.surfile_rb_t (surfile_rb_t),
.surfile_rb_f (surfile_rb_f),
.surdamux (surdamux),
.surdbmux (surdbmux),
.suimmmux (suimmmux),
.suimmlsmux (suimmlsmux),
.suvulsoffsetmux (suvulsoffsetmux),
.set_broke (set_broke),
.break_inst_debug (break_inst_debug),
.sualuamux (sualuamux[1:0]),
.sualubmux (sualubmux[1:0]),
.sushamux (sushamux),
.sushbmux (sushbmux),
.sudrivels (sudrivels),
.suslten (suslten),
.susltlt (susltlt),
.sualuen (sualuen),
.sualu (sualu[4:0]),
.sualu_cin (sualu_cin),
.sushen (sushen),
.shiftamt (shiftamt[31:0]),
.sushift_s (sushift_s),
.su_ex_store (su_ex_store),
.su_ex_load (su_ex_load),
.vu_ex_store (vu_ex_store),
.vu_ex_load (vu_ex_load),
.ex_mfc2 (ex_mfc2),
.ex_mtc2 (ex_mtc2),
.ex_cfc2 (ex_cfc2),
.ex_su_byte_ls (ex_su_byte_ls),
.ex_su_half_ls (ex_su_half_ls),
.ex_su_uns_ls (ex_su_uns_ls),
.elem_num (elem_num[3:0]),
.chip_sel (chip_sel),
.vu_rd_ld_dec_k (vu_rd_ld_dec_k),
.vu_rd_st_dec_k (vu_rd_st_dec_k),
.df_ls_drive_ls_in_wb (df_ls_drive_ls_in_wb),
.df_pass_thru (df_pass_thru),
.surfile_w_t (surfile_w_t),
.surfile_w_f (surfile_w_f),
.su_mem_wen (su_mem_wen),
.suwben (suwben),
.vu_comp_k (vu_comp_k),
.vu_func (vu_func),
.vs_eq_one (vs_eq_one),
.vu_elem (vu_elem),
.vs (vs),
.ex_ctc2_vc0 (ex_ctc2_vc0),
.ex_ctc2_vc1 (ex_ctc2_vc1),
.ex_ctc2_vc2 (ex_ctc2_vc2),
.vu_rd_store_type_k (vu_rd_store_type_k),
.vu_rd_storecfc2_k (vu_rd_storecfc2_k),
.rd_cfvc0_k (rd_cfvc0_k),
.rd_cfvc1_k (rd_cfvc1_k),
.rd_cfvc2_k (rd_cfvc2_k),
.acc_wr_reg (acc_wr_reg),
.acc_wr_en (acc_wr_en),
.vu_ld_addr (vu_ld_addr),
.vu_st_addr (vu_st_addr),
.vu_st_xpose_addr (vu_st_xpose_addr),
.xpose (xpose),
.rd_pre_vt (rd_pre_vt),
.vt_sel (vt_sel),
.cp0_address (cp0_address),
.cp0_write (cp0_write),
.cp0_enable (cp0_enable),
.ex_mfc0 (ex_mfc0),
.imem_chip_sel_l (imem_chip_sel_l),
.imem_dma_cycle (imem_dma_cycle),
.su_nop_debug (su_nop_debug),
.vu_nop_debug (vu_nop_debug),
.link_pc_delay_pc (link_pc_delay_pc),
.pc (pc)
);
vt_decode vt_decode (
.vt_rd_inst_h (rd_inst[52:48]),
.vt_rd_inst_l (rd_inst[20:16]),
.vt_else (rd_pre_vt),
.vt_rd_inst_h_sel (vt_sel[0]),
.vt_rd_inst_l_sel (vt_sel[1]),
.branch_or_addr_unbuf (branch_or_addr_unbuf),
.su_inst_6_unbuf (su_inst[6]),
.su_inst_15_unbuf (su_inst[15]),
.vt_decoded_a (vt_decoded_a),
.vt_decoded_b (vt_decoded_b),
.branch_or_addr (branch_or_addr),
.su_inst_6 (su_inst_6),
.su_inst_15 (su_inst_15)
);
endmodule